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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [tick/] [tick.c] - Diff between revs 538 and 561

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Rev 538 Rev 561
Line 47... Line 47...
#include "sim-config.h"
#include "sim-config.h"
#include "sched.h"
#include "sched.h"
 
 
 
 
/*! When did the timer start to count */
/*! When did the timer start to count */
static long long cycles_start = 0;
static long long cycle_count_at_tick_start = 0;
 
 
/*! Indicates if the timer is actually counting.  Needed to simulate one-shot
/*! Indicates if the timer is actually counting.  Needed to simulate one-shot
    mode correctly */
    mode correctly */
int tick_count;
int tick_counting;
 
 
/*! Reset. It initializes TTCR register. */
/*! Reset. It initializes TTCR register. */
void
void
tick_reset (void)
tick_reset (void)
{
{
Line 64... Line 64...
      PRINTF ("Resetting Tick Timer.\n");
      PRINTF ("Resetting Tick Timer.\n");
    }
    }
 
 
  cpu_state.sprs[SPR_TTCR] = 0;
  cpu_state.sprs[SPR_TTCR] = 0;
  cpu_state.sprs[SPR_TTMR] = 0;
  cpu_state.sprs[SPR_TTMR] = 0;
  tick_count = 0;
  tick_counting = 0;
}
}
 
 
/*! Raises a timer exception */
/*! Raises a timer exception */
static void
static void
tick_raise_except (void *dat)
tick_raise_except (void *dat)
Line 89... Line 89...
/*! Restarts the tick timer */
/*! Restarts the tick timer */
static void
static void
tick_restart (void *dat)
tick_restart (void *dat)
{
{
  cpu_state.sprs[SPR_TTCR] = 0;
  cpu_state.sprs[SPR_TTCR] = 0;
  cycles_start = runtime.sim.cycles;
  cycle_count_at_tick_start = runtime.sim.cycles;
  SCHED_ADD (tick_restart, NULL, cpu_state.sprs[SPR_TTMR] & SPR_TTMR_TP);
  SCHED_ADD (tick_restart, NULL, cpu_state.sprs[SPR_TTMR] & SPR_TTMR_TP);
}
}
 
 
/*! Stops the timer */
/*! Stops the timer */
static void
static void
tick_one_shot (void *dat)
tick_one_shot (void *dat)
{
{
  cpu_state.sprs[SPR_TTCR] = cpu_state.sprs[SPR_TTMR] & SPR_TTMR_TP;
  cpu_state.sprs[SPR_TTCR] = cpu_state.sprs[SPR_TTMR] & SPR_TTMR_TP;
  tick_count = 0;
  tick_counting = 0;
}
}
 
 
/*! Schedules the timer jobs */
/*! Schedules the timer jobs */
static void
static void
sched_timer_job (uorreg_t prev_ttmr)
sched_timer_job (uorreg_t prev_ttmr)
{
{
  uorreg_t ttmr = cpu_state.sprs[SPR_TTMR];
  uorreg_t ttmr = cpu_state.sprs[SPR_TTMR];
  uint32_t match_time = ttmr & SPR_TTMR_TP;
  uint32_t match_ttmr = ttmr & SPR_TTMR_TP;
  uint32_t ttcr_period = spr_read_ttcr () & SPR_TTCR_CNT;
  /* TTCR register, only concerned with part of TTCR which will trigger int */
 
  uint32_t match_ttcr = spr_read_ttcr () & SPR_TTMR_TP;
 
  uint32_t cycles_until_except;
 
 
  /* Remove previous jobs if they exists */
  /* On clearing TTMR interrupt signal bit remove previous jobs if they
 
     exist */
  if ((prev_ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
  if ((prev_ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
    {
    {
      SCHED_FIND_REMOVE (tick_raise_except, NULL);
      SCHED_FIND_REMOVE (tick_raise_except, NULL);
    }
    }
 
 
Line 126... Line 129...
    case SPR_TTMR_SR:
    case SPR_TTMR_SR:
      SCHED_FIND_REMOVE (tick_one_shot, NULL);
      SCHED_FIND_REMOVE (tick_one_shot, NULL);
      break;
      break;
    }
    }
 
 
  if (match_time >= ttcr_period)
  /* Calculate cycles until next tick exception, based on current TTCR value */
 
  if (match_ttmr >= match_ttcr)
    {
    {
      match_time -= ttcr_period;
      cycles_until_except = match_ttmr - match_ttcr;
    }
    }
  else
  else
    {
    {
      match_time += (0xfffffffu - ttcr_period) + 1;
      /* Cycles after "wrap" of section of TTCR which will cause a match and,
 
         potentially, an exception */
 
      cycles_until_except = match_ttmr + (0x0fffffffu - match_ttcr) + 1;
    }
    }
 
 
  switch (ttmr & SPR_TTMR_M)
  switch (ttmr & SPR_TTMR_M)
    {
    {
    case 0:                      /* Disabled timer */
    case 0:                      /* Disabled timer */
      if (!match_time && (ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
      if (!cycles_until_except && (ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
        SCHED_ADD (tick_raise_except, NULL, 0);
        SCHED_ADD (tick_raise_except, NULL, 0);
      break;
      break;
 
 
    case SPR_TTMR_RT:           /* Auto-restart timer */
    case SPR_TTMR_RT:           /* Auto-restart timer */
      SCHED_ADD (tick_restart, NULL, match_time);
      SCHED_ADD (tick_restart, NULL, cycles_until_except);
      if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
      if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
        SCHED_ADD (tick_raise_except, NULL, match_time);
        SCHED_ADD (tick_raise_except, NULL, cycles_until_except);
      break;
      break;
 
 
    case SPR_TTMR_SR:           /* One-shot timer */
    case SPR_TTMR_SR:           /* One-shot timer */
      if (tick_count)
      if (tick_counting)
        {
        {
          SCHED_ADD (tick_one_shot, NULL, match_time);
          SCHED_ADD (tick_one_shot, NULL, cycles_until_except);
          if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
          if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
            SCHED_ADD (tick_raise_except, NULL, match_time);
            SCHED_ADD (tick_raise_except, NULL, cycles_until_except);
        }
        }
      break;
      break;
 
 
    case SPR_TTMR_CR:           /* Continuos timer */
    case SPR_TTMR_CR:           /* Continuos timer */
      if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
      if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
        SCHED_ADD (tick_raise_except, NULL, match_time);
        SCHED_ADD (tick_raise_except, NULL, cycles_until_except);
    }
    }
}
}
 
 
 
 
/*! Handles a write to the ttcr spr */
/*! Handles a write to the ttcr spr */
void
void
spr_write_ttcr (uorreg_t value)
spr_write_ttcr (uorreg_t value)
{
{
  cycles_start = runtime.sim.cycles - value;
  cycle_count_at_tick_start = runtime.sim.cycles - value;
 
 
  sched_timer_job (cpu_state.sprs[SPR_TTMR]);
  sched_timer_job (cpu_state.sprs[SPR_TTMR]);
}
}
 
 
/*! Value is the *previous* value of SPR_TTMR.  The new one can be found in
/*! prev_val is the *previous* value of SPR_TTMR.  The new one can be found in
    cpu_state.sprs[SPR_TTMR] */
    cpu_state.sprs[SPR_TTMR] */
void
void
spr_write_ttmr (uorreg_t prev_val)
spr_write_ttmr (uorreg_t prev_val)
{
{
  uorreg_t value = cpu_state.sprs[SPR_TTMR];
  uorreg_t value = cpu_state.sprs[SPR_TTMR];
 
 
  /* Code running on or1k can't set SPR_TTMR_IP so make sure it isn't */
  /* Code running on or1k can't set SPR_TTMR_IP so make sure it isn't */
  cpu_state.sprs[SPR_TTMR] &= ~SPR_TTMR_IP;
  cpu_state.sprs[SPR_TTMR] &= ~SPR_TTMR_IP;
 
 
  /* If the timer was already disabled, ttcr should not be updated */
  /* If the timer was already disabled, ttcr should not be updated */
  if (tick_count)
  if (tick_counting)
    {
    {
      cpu_state.sprs[SPR_TTCR] = runtime.sim.cycles - cycles_start;
      cpu_state.sprs[SPR_TTCR] = runtime.sim.cycles - cycle_count_at_tick_start;
    }
    }
 
 
  cycles_start = runtime.sim.cycles - cpu_state.sprs[SPR_TTCR];
  cycle_count_at_tick_start = runtime.sim.cycles - cpu_state.sprs[SPR_TTCR];
 
 
  tick_count = value & SPR_TTMR_M;
  tick_counting = value & SPR_TTMR_M;
 
 
  if ((tick_count == 0xc0000000) &&
  /* If TTCR==TTMR_TP when setting MR, we disable counting??
 
     I think this should be looked at - Julius */
 
  if ((tick_counting == SPR_TTMR_CR) &&
      (cpu_state.sprs[SPR_TTCR] == (value & SPR_TTMR_TP)))
      (cpu_state.sprs[SPR_TTCR] == (value & SPR_TTMR_TP)))
    {
    {
      tick_count = 0;
      tick_counting = 0;
    }
    }
 
 
  sched_timer_job (prev_val);
  sched_timer_job (prev_val);
}
}
 
 
uorreg_t
uorreg_t
spr_read_ttcr ()
spr_read_ttcr ()
{
{
  uorreg_t ret;
  uorreg_t ret;
 
 
  if (!tick_count)
  if (!tick_counting)
    {
    {
      /* Report the time when the counter stoped (and don't carry on
      /* Report the time when the counter stopped (and don't carry on
         counting) */
         counting) */
      ret = cpu_state.sprs[SPR_TTCR];
      ret = cpu_state.sprs[SPR_TTCR];
    }
    }
  else
  else
    {
    {
      ret = runtime.sim.cycles - cycles_start;
      ret = runtime.sim.cycles - cycle_count_at_tick_start;
    }
    }
 
 
  return  ret;
  return  ret;
}
}
 
 
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