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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [toplevel-support.c] - Diff between revs 230 and 235

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Rev 230 Rev 235
Line 47... Line 47...
#include "execute.h"
#include "execute.h"
#include "labels.h"
#include "labels.h"
#include "stats.h"
#include "stats.h"
#include "opcode/or32.h"
#include "opcode/or32.h"
#include "parse.h"
#include "parse.h"
#include "gdbcomm.h"
 
#include "rsp-server.h"
#include "rsp-server.h"
#include "vapi.h"
#include "vapi.h"
#include "abstract.h"
#include "abstract.h"
#include "mc.h"
#include "mc.h"
#include "except.h"
#include "except.h"
Line 298... Line 297...
                   runtime.sim.filename);
                   runtime.sim.filename);
          exit (1);
          exit (1);
        }
        }
    }
    }
 
 
  /* Disable GDB debugging, if debug unit is not available.  */
  /* Disable RSP debugging, if debug unit is not available.  */
  if ((config.debug.gdb_enabled || config.debug.rsp_enabled) &&
  if (config.debug.rsp_enabled && !config.debug.enabled)
      !config.debug.enabled)
 
    {
    {
      config.debug.gdb_enabled = 0;
 
      config.debug.rsp_enabled = 0;
      config.debug.rsp_enabled = 0;
 
 
      if (config.sim.verbose)
      if (config.sim.verbose)
        {
        {
          fprintf (stderr, "WARNING: sim_init: Debug module not enabled, "
          fprintf (stderr, "WARNING: sim_init: Debug module not enabled, "
Line 322... Line 319...
      /* RSP always starts stalled as though we have just reset the
      /* RSP always starts stalled as though we have just reset the
         processor. */
         processor. */
      rsp_exception (EXCEPT_TRAP);
      rsp_exception (EXCEPT_TRAP);
      set_stall_state (1);
      set_stall_state (1);
    }
    }
  else if (config.debug.gdb_enabled)
 
    {
 
      gdbcomm_init ();
 
    }
 
 
 
  /* Enable dependency stats, if we want to do history analisis */
  /* Enable dependency stats, if we want to do history analisis */
  if (config.sim.history && !config.cpu.dependstats)
  if (config.sim.history && !config.cpu.dependstats)
    {
    {
      config.cpu.dependstats = 1;
      config.cpu.dependstats = 1;

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