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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
[/] [openrisc/] [trunk/] [or1ksim/] [toplevel-support.c] - Diff between revs 230 and 235
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| Rev 230 |
Rev 235 |
| Line 47... |
Line 47... |
#include "execute.h"
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#include "execute.h"
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#include "labels.h"
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#include "labels.h"
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#include "stats.h"
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#include "stats.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "parse.h"
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#include "parse.h"
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#include "gdbcomm.h"
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#include "rsp-server.h"
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#include "rsp-server.h"
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#include "vapi.h"
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#include "vapi.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "mc.h"
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#include "mc.h"
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#include "except.h"
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#include "except.h"
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| Line 298... |
Line 297... |
runtime.sim.filename);
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runtime.sim.filename);
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exit (1);
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exit (1);
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}
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}
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}
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}
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/* Disable GDB debugging, if debug unit is not available. */
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/* Disable RSP debugging, if debug unit is not available. */
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if ((config.debug.gdb_enabled || config.debug.rsp_enabled) &&
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if (config.debug.rsp_enabled && !config.debug.enabled)
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!config.debug.enabled)
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{
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{
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config.debug.gdb_enabled = 0;
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config.debug.rsp_enabled = 0;
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config.debug.rsp_enabled = 0;
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if (config.sim.verbose)
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if (config.sim.verbose)
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{
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{
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fprintf (stderr, "WARNING: sim_init: Debug module not enabled, "
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fprintf (stderr, "WARNING: sim_init: Debug module not enabled, "
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| Line 322... |
Line 319... |
/* RSP always starts stalled as though we have just reset the
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/* RSP always starts stalled as though we have just reset the
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processor. */
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processor. */
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rsp_exception (EXCEPT_TRAP);
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rsp_exception (EXCEPT_TRAP);
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set_stall_state (1);
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set_stall_state (1);
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}
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}
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else if (config.debug.gdb_enabled)
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{
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gdbcomm_init ();
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}
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/* Enable dependency stats, if we want to do history analisis */
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/* Enable dependency stats, if we want to do history analisis */
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if (config.sim.history && !config.cpu.dependstats)
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if (config.sim.history && !config.cpu.dependstats)
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{
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{
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config.cpu.dependstats = 1;
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config.cpu.dependstats = 1;
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