URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or_debug_proxy/] [includes/] [or_debug_proxy.h] - Diff between revs 79 and 94

Rev 79	Rev 94
Line 130...	Line 130...
`int dbg_set_tap_ir(uint32_t ir);`	`int dbg_set_tap_ir(uint32_t ir);`
`/* Set "scan chain" of debug unit (NOT JTAG TAP!) */`	`/* Set "scan chain" of debug unit (NOT JTAG TAP!) */`
`int dbg_set_chain(uint32_t chain);`	`int dbg_set_chain(uint32_t chain);`
`/* read a byte from wishbone */`	`/* read a byte from wishbone */`
`int dbg_wb_write8(uint32_t adr, uint8_t data);`	`int dbg_wb_write8(uint32_t adr, uint8_t data);`
	`/* read a byte from wishbone */`
	`int dbg_wb_read8(uint32_t adr, uint8_t *data);`
`/* read a word from wishbone */`	`/* read a word from wishbone */`
`int dbg_wb_read32(uint32_t adr, uint32_t *data);`	`int dbg_wb_read32(uint32_t adr, uint32_t *data);`
`/* write a word to wishbone */`	`/* write a word to wishbone */`
`int dbg_wb_write32(uint32_t adr, uint32_t data);`	`int dbg_wb_write32(uint32_t adr, uint32_t data);`
`/* read a block from wishbone */`	`/* read a block from wishbone */`