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//! This class is based on the or1200_monitor.v of the Verilog test bench. It
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//! This class is based on the or1200_monitor.v of the Verilog test bench. It
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//! wakes up on each posedge clock to check for "special" l.nop instructions,
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//! wakes up on each posedge clock to check for "special" l.nop instructions,
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//! which need processing.
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//! which need processing.
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class Or1200MonitorSC
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class Or1200MonitorSC:public sc_core::sc_module {
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: public sc_core::sc_module
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{
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public:
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public:
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// Constructor
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// Constructor
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Or1200MonitorSC (sc_core::sc_module_name name,
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Or1200MonitorSC (sc_core::sc_module_name name,
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OrpsocAccess *_accessor,
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OrpsocAccess *_accessor,
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MemoryLoad *_memoryload,
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MemoryLoad * _memoryload, int argc, char *argv[]);
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int argc,
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char *argv[]);
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// Method to check instructions
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// Method to check instructions
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void checkInstruction();
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void checkInstruction();
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// Methods to setup and output state of processor to a file
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// Methods to setup and output state of processor to a file
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void displayState();
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void displayState();
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void displayStateBinary();
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void displayStateBinary();
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// Methods to generate trace to stdout
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void printTrace();
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// Methods to generate the call and return list during execution
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// Methods to generate the call and return list during execution
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void callLog();
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void callLog();
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// Method to calculate performance of the sim
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// Method to calculate performance of the sim
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void perfSummary();
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void perfSummary();
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//void busMonitor();
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//void busMonitor();
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// Method to do simulator assisted printf'ing
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// Method to do simulator assisted printf'ing
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void simPrintf(uint32_t stackaddr, uint32_t regparam);
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void simPrintf(uint32_t stackaddr, uint32_t regparam);
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// The ports
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// The ports
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sc_in<bool> clk;
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sc_in<bool> clk;
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private:
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private:
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#define DEFAULT_PROF_FILE "sim.profile"
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#define DEFAULT_PROF_FILE "sim.profile"
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#define DEFAULT_MEMDUMP_FILE "vorpsoc_ram.dump"
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#define DEFAULT_MEMDUMP_FILE "vorpsoc_ram.dump"
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#define DEFAULT_BUS_LOG_FILE "bus_trans.log"
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#define DEFAULT_BUS_LOG_FILE "bus_trans.log"
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// Special NOP instructions
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// Special NOP instructions
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static const uint32_t NOP_NOP = 0x15000000; //!< Normal nop instruction
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static const uint32_t NOP_NOP = 0; //!< Normal nop instruction
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static const uint32_t NOP_EXIT = 0x15000001; //!< End of simulation
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static const uint32_t NOP_EXIT = 1; //!< End of simulation
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static const uint32_t NOP_REPORT = 0x15000002; //!< Simple report
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static const uint32_t NOP_REPORT = 2; //!< Simple report
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static const uint32_t NOP_PRINTF = 0x15000003; //!< Simprintf instruction
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static const uint32_t NOP_PRINTF = 3; //!< Simprintf instruction
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static const uint32_t NOP_PUTC = 0x15000004; //!< Putc instruction
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static const uint32_t NOP_PUTC = 4; //!< Putc instruction
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static const uint32_t NOP_CNT_RESET = 0x15000005; //!< Reset statistics counters
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static const uint32_t NOP_CNT_RESET = 5; //!< Reset statistics counters
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static const uint32_t NOP_CNT_RESET1 = 0x15000007; /* Reset statistics counter 1 */
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static const uint32_t NOP_GET_TICKS = 6; //!< Get # ticks running
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static const uint32_t NOP_CNT_RESET2 = 0x15000008; /* Reset statistics counter 2 */
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static const uint32_t NOP_GET_PS = 7; //!< Get picosecs/cycle
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static const uint32_t NOP_CNT_RESET3 = 0x15000009; /* Reset statistics counter 3 */
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static const uint32_t NOP_MEM_STATS_RESET = 0x15000010; //!< Reset memory statistics counters
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static const uint32_t NOP_CNT_RESET1 = 16; /* Reset statistics counter 1 */
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static const uint32_t NOP_CNT_RESET_DIFFERENCE = 0x15000006; //!< Reset stats counters, print
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static const uint32_t NOP_CNT_RESET2 = 17; /* Reset statistics counter 2 */
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static const uint32_t NOP_CNT_RESET3 = 18; /* Reset statistics counter 3 */
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static const uint32_t NOP_MEM_STATS_RESET = 32; //!< Reset memory statistics counters
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static const uint32_t NOP_CNT_RESET_DIFFERENCE = 48; //!< Reset stats counters, print
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// Variables for processor status output
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// Variables for processor status output
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ofstream statusFile;
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ofstream statusFile;
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ofstream profileFile;
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ofstream profileFile;
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bool profiling_enabled;
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bool profiling_enabled;
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bool trace_enabled;
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bool logging_enabled;
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bool logging_enabled;
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bool logfile_name_provided;
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bool logfile_name_provided;
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bool logging_regs;
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bool logging_regs;
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bool binary_log_format;
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bool binary_log_format;
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bool quiet;
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bool perf_summary;
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bool monitor_for_crash;
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bool monitor_for_crash;
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int lookslikewevecrashed_count, crash_monitor_buffer_head;
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int lookslikewevecrashed_count, crash_monitor_buffer_head;
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#define CRASH_MONITOR_BUFFER_SIZE 32
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#define CRASH_MONITOR_BUFFER_SIZE 32
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uint32_t crash_monitor_buffer[CRASH_MONITOR_BUFFER_SIZE][2]; //PC, Insn
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uint32_t crash_monitor_buffer[CRASH_MONITOR_BUFFER_SIZE][2]; //PC, Insn
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bool wait_for_stall_cmd_response;
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bool wait_for_stall_cmd_response;
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unsigned long long cycles_1, cycles_2, cycles_3; // Cycle counters for l.nop insns
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unsigned long long cycles_1, cycles_2, cycles_3; // Cycle counters for l.nop insns
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ofstream memdumpFile;
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ofstream memdumpFile;
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string memdumpFileName;
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string memdumpFileName;
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bool do_memdump;
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bool do_memdump;
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int memdump_start_addr, memdump_end_addr;
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int memdump_start_addr, memdump_end_addr;
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bool bus_trans_log_enabled, bus_trans_log_name_provided, bus_trans_log_start_delay_enable;
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bool bus_trans_log_enabled, bus_trans_log_name_provided,
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bus_trans_log_start_delay_enable;
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sc_time bus_trans_log_start_delay;
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sc_time bus_trans_log_start_delay;
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enum busLogStates { BUS_LOG_IDLE, BUS_LOG_WAIT_FOR_ACK };
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enum busLogStates { BUS_LOG_IDLE, BUS_LOG_WAIT_FOR_ACK };
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ofstream busTransLog;
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ofstream busTransLog;
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//! Time measurement variable - for calculating performance of the sim
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//! Time measurement variable - for calculating performance of the sim
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