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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [Or1200MonitorSC.h] - Diff between revs 435 and 462

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Rev 435 Rev 462
Line 42... Line 42...
 
 
//! This class is based on the or1200_monitor.v of the Verilog test bench. It
//! This class is based on the or1200_monitor.v of the Verilog test bench. It
//! wakes up on each posedge clock to check for "special" l.nop instructions,
//! wakes up on each posedge clock to check for "special" l.nop instructions,
//! which need processing.
//! which need processing.
 
 
class Or1200MonitorSC
class Or1200MonitorSC:public sc_core::sc_module {
  : public sc_core::sc_module
 
{
 
public:
public:
 
 
  // Constructor
  // Constructor
  Or1200MonitorSC (sc_core::sc_module_name  name,
  Or1200MonitorSC (sc_core::sc_module_name  name,
                   OrpsocAccess            *_accessor,
                   OrpsocAccess            *_accessor,
                   MemoryLoad              *_memoryload,
                        MemoryLoad * _memoryload, int argc, char *argv[]);
                   int argc,
 
                   char *argv[]);
 
 
 
  // Method to check instructions
  // Method to check instructions
  void  checkInstruction();
  void  checkInstruction();
 
 
  // Methods to setup and output state of processor to a file
  // Methods to setup and output state of processor to a file
  void displayState();
  void displayState();
  void displayStateBinary();
  void displayStateBinary();
 
 
 
        // Methods to generate trace to stdout
 
        void printTrace();
 
 
  // Methods to generate the call and return list during execution
  // Methods to generate the call and return list during execution
  void callLog();
  void callLog();
 
 
  // Method to calculate performance of the sim
  // Method to calculate performance of the sim
  void perfSummary();
  void perfSummary();
Line 82... Line 81...
  //void busMonitor();
  //void busMonitor();
 
 
  // Method to do simulator assisted printf'ing
  // Method to do simulator assisted printf'ing
  void simPrintf(uint32_t stackaddr, uint32_t regparam);
  void simPrintf(uint32_t stackaddr, uint32_t regparam);
 
 
 
 
 
 
  // The ports
  // The ports
  sc_in<bool>   clk;
  sc_in<bool>   clk;
 
 
private:
private:
 
 
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#define DEFAULT_PROF_FILE "sim.profile"
#define DEFAULT_PROF_FILE "sim.profile"
#define DEFAULT_MEMDUMP_FILE "vorpsoc_ram.dump"
#define DEFAULT_MEMDUMP_FILE "vorpsoc_ram.dump"
#define DEFAULT_BUS_LOG_FILE "bus_trans.log"
#define DEFAULT_BUS_LOG_FILE "bus_trans.log"
 
 
  // Special NOP instructions
  // Special NOP instructions
  static const uint32_t NOP_NOP    = 0x15000000;  //!< Normal nop instruction
        static const uint32_t NOP_NOP = 0;       //!< Normal nop instruction
  static const uint32_t NOP_EXIT   = 0x15000001;  //!< End of simulation
        static const uint32_t NOP_EXIT = 1;     //!< End of simulation
  static const uint32_t NOP_REPORT = 0x15000002;  //!< Simple report
        static const uint32_t NOP_REPORT = 2;   //!< Simple report
  static const uint32_t NOP_PRINTF = 0x15000003;  //!< Simprintf instruction
        static const uint32_t NOP_PRINTF = 3;   //!< Simprintf instruction
  static const uint32_t NOP_PUTC   = 0x15000004;  //!< Putc instruction
        static const uint32_t NOP_PUTC = 4;     //!< Putc instruction
  static const uint32_t NOP_CNT_RESET = 0x15000005; //!< Reset statistics counters
        static const uint32_t NOP_CNT_RESET = 5;        //!< Reset statistics counters
  static const uint32_t NOP_CNT_RESET1 = 0x15000007;        /* Reset statistics counter 1 */
        static const uint32_t NOP_GET_TICKS = 6;        //!< Get # ticks running
  static const uint32_t NOP_CNT_RESET2 = 0x15000008;        /* Reset statistics counter 2 */
        static const uint32_t NOP_GET_PS = 7;   //!< Get picosecs/cycle
  static const uint32_t NOP_CNT_RESET3 = 0x15000009;        /* Reset statistics counter 3 */
 
  static const uint32_t NOP_MEM_STATS_RESET  = 0x15000010; //!< Reset memory statistics counters
        static const uint32_t NOP_CNT_RESET1 = 16;      /* Reset statistics counter 1 */
  static const uint32_t NOP_CNT_RESET_DIFFERENCE = 0x15000006; //!< Reset stats counters, print 
        static const uint32_t NOP_CNT_RESET2 = 17;      /* Reset statistics counter 2 */
 
        static const uint32_t NOP_CNT_RESET3 = 18;      /* Reset statistics counter 3 */
 
        static const uint32_t NOP_MEM_STATS_RESET = 32; //!< Reset memory statistics counters
 
        static const uint32_t NOP_CNT_RESET_DIFFERENCE = 48;    //!< Reset stats counters, print 
 
 
  // Variables for processor status output
  // Variables for processor status output
  ofstream statusFile;
  ofstream statusFile;
  ofstream profileFile;
  ofstream profileFile;
  bool profiling_enabled;
  bool profiling_enabled;
 
        bool trace_enabled;
  bool logging_enabled;
  bool logging_enabled;
  bool logfile_name_provided;
  bool logfile_name_provided;
  bool logging_regs;
  bool logging_regs;
  bool binary_log_format;
  bool binary_log_format;
  bool quiet;
        bool perf_summary;
  bool monitor_for_crash;
  bool monitor_for_crash;
  int lookslikewevecrashed_count, crash_monitor_buffer_head;
  int lookslikewevecrashed_count, crash_monitor_buffer_head;
#define CRASH_MONITOR_BUFFER_SIZE 32
#define CRASH_MONITOR_BUFFER_SIZE 32
  uint32_t crash_monitor_buffer[CRASH_MONITOR_BUFFER_SIZE][2]; //PC, Insn
  uint32_t crash_monitor_buffer[CRASH_MONITOR_BUFFER_SIZE][2]; //PC, Insn
  bool wait_for_stall_cmd_response;
  bool wait_for_stall_cmd_response;
Line 128... Line 129...
  unsigned long long cycles_1, cycles_2, cycles_3; // Cycle counters for l.nop insns
  unsigned long long cycles_1, cycles_2, cycles_3; // Cycle counters for l.nop insns
  ofstream memdumpFile;
  ofstream memdumpFile;
  string memdumpFileName;
  string memdumpFileName;
  bool do_memdump;
  bool do_memdump;
  int memdump_start_addr, memdump_end_addr;
  int memdump_start_addr, memdump_end_addr;
  bool bus_trans_log_enabled, bus_trans_log_name_provided, bus_trans_log_start_delay_enable;
        bool bus_trans_log_enabled, bus_trans_log_name_provided,
 
            bus_trans_log_start_delay_enable;
  sc_time bus_trans_log_start_delay;
  sc_time bus_trans_log_start_delay;
  enum busLogStates { BUS_LOG_IDLE, BUS_LOG_WAIT_FOR_ACK };
  enum busLogStates { BUS_LOG_IDLE, BUS_LOG_WAIT_FOR_ACK };
  ofstream busTransLog;
  ofstream busTransLog;
 
 
  //! Time measurement variable - for calculating performance of the sim
  //! Time measurement variable - for calculating performance of the sim

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