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//! System's internal RAM size in byes - found in rtl/verilog/orpsoc_top.v, param for ram_wb module
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//! System's internal RAM size in byes - found in rtl/verilog/orpsoc_top.v, param for ram_wb module
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//! Currently is 32MB (8M words)
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//! Currently is 32MB (8M words)
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#define ORPSOC_SRAM_SIZE (8388608*4)
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#define ORPSOC_SRAM_SIZE (8388608*4)
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//! Ratio of JTAG clock period to CPU clock period
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#define CLOCK_RATIO 10
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//! JTAG clock half period in timescale units
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#define JTAG_CLK_HALFPERIOD (CLOCK_RATIO * BENCH_CLK_HALFPERIOD)
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//! Start of 2MB Flash memory
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#define FLASH_START 0xf0000000
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//! End of 2MB Flash memory
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#define FLASH_END 0xf01fffff
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//! Default port for RSP to listen on
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#define DEFAULT_RSP_PORT 51000
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//! FIFO size for talking to the RSP connection
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#define RSP_FIFO_SIZE 8
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//! Maximum size of a RSP packet is used to return the value of all the
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//! registers, each of which takes 8 chars. There are a total of 32 GPRs plus
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//! PPC, SR and NPC. Plus one byte for end of string marker.
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#define RSP_MAX_PKT_SIZE ((32 + 3) * 8 + 1)
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#endif // ORPSOC_MAIN__H
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#endif // ORPSOC_MAIN__H
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