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Rev 354 |
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//! The number of cycles of reset required
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//! The number of cycles of reset required
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#define BENCH_RESET_TIME 10
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#define BENCH_RESET_TIME 10
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//! CPU clock Half period in timescale units
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//! CPU clock Half period in timescale units
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#define BENCH_CLK_HALFPERIOD 20
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#define BENCH_CLK_HALFPERIOD 10
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//! System's internal RAM size in byes - found in rtl/verilog/orpsoc_top.v, param for ram_wb module
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//! System's internal RAM size in byes - found in rtl/verilog/orpsoc_top.v, param for ram_wb module
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//! Currently is 32MB (8M words)
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//! Currently is 32MB (8M words)
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#define ORPSOC_SRAM_SIZE (8388608*4)
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#define ORPSOC_SRAM_SIZE (8388608*4)
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//! End of 2MB Flash memory
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//! End of 2MB Flash memory
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#define FLASH_END 0xf01fffff
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#define FLASH_END 0xf01fffff
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//! Default port for RSP to listen on
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//! Default port for RSP to listen on
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#define DEFAULT_RSP_PORT 51000
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#define DEFAULT_RSP_PORT 50003
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//! FIFO size for talking to the RSP connection
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//! FIFO size for talking to the RSP connection
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#define RSP_FIFO_SIZE 8
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#define RSP_FIFO_SIZE 8
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//! Maximum size of a RSP packet is used to return the value of all the
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//! Maximum size of a RSP packet is used to return the value of all the
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