OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [OrpsocMain.h] - Diff between revs 354 and 462

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 354 Rev 462
Line 44... Line 44...
// consistent with the values used in the Verilog
// consistent with the values used in the Verilog
 
 
#ifndef ORPSOC_MAIN__H
#ifndef ORPSOC_MAIN__H
#define ORPSOC_MAIN__H
#define ORPSOC_MAIN__H
 
 
 
/* Globals used by other C modules */
 
extern bool gQuiet;
 
extern int gSimRunning;
 
 
//! The Verilog timescale unit (as SystemC timescale unit)
//! The Verilog timescale unit (as SystemC timescale unit)
#define TIMESCALE_UNIT        SC_NS
#define TIMESCALE_UNIT        SC_NS
 
 
//! The number of cycles of reset required
//! The number of cycles of reset required
#define BENCH_RESET_TIME      10
#define BENCH_RESET_TIME      10
 
 
//! CPU clock Half period in timescale units
//! CPU clock Half period in timescale units
#define BENCH_CLK_HALFPERIOD  10
#define BENCH_CLK_HALFPERIOD  10
 
 
//! System's internal RAM size in byes - found in rtl/verilog/orpsoc_top.v, param for ram_wb module
 
//! Currently is 32MB (8M words)
 
#define ORPSOC_SRAM_SIZE (8388608*4)
 
 
 
//! Ratio of JTAG clock period to CPU clock period
//! Ratio of JTAG clock period to CPU clock period
#define CLOCK_RATIO  10
#define CLOCK_RATIO  10
 
 
//! JTAG clock half period in timescale units
//! JTAG clock half period in timescale units
#define JTAG_CLK_HALFPERIOD (CLOCK_RATIO * BENCH_CLK_HALFPERIOD)
#define JTAG_CLK_HALFPERIOD (CLOCK_RATIO * BENCH_CLK_HALFPERIOD)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.