URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 462 |
Rev 500 |
Line 40... |
Line 40... |
sc_in < bool > clk;
|
sc_in < bool > clk;
|
sc_in < bool > uarttx;
|
sc_in < bool > uarttx;
|
sc_out < bool > uartrx;
|
sc_out < bool > uartrx;
|
|
|
// Init function
|
// Init function
|
void initUart(int clk_freq_hz, int uart_baud);
|
void initUart(int uart_baud);
|
// Transmit (from ORPSoC) handling function
|
// Transmit (from ORPSoC) handling function
|
void checkTx();
|
void checkTx();
|
|
// Receieve (in ORPSoC) generation function
|
|
void driveRx();
|
|
// Check keyboard for entry
|
|
int kbhit();
|
|
// Enable canonical mode on console
|
|
void nonblock(int state);
|
|
|
private:
|
private:
|
int clocks_per_bit;
|
|
uint8_t current_char;
|
uint8_t current_char;
|
int counter;
|
int counter;
|
int bits_received;
|
int bits_received;
|
|
int ns_per_bit;
|
|
|
|
int rx_state;
|
|
int rx_counter;
|
|
int rx_bits_sent;
|
|
char rx_char;
|
|
|
}; // UartSC ()
|
}; // UartSC ()
|
|
|
#endif // UART_SC__H
|
#endif // UART_SC__H
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.