Subversion Repositories openrisc_2011-10-31

#include <iomanip>

#include <iomanip>

#include "DebugUnitSC.h"

#include "DebugUnitSC.h"

#include "Utils.h"

#include "Utils.h"

using sc_core::sc_event;

using sc_core::sc_event;

using sc_core::sc_fifo;

using sc_core::sc_fifo;

using sc_core::sc_module_name;

using sc_core::sc_module_name;

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Constructor for the Debug Unit

//! Constructor for the Debug Unit

//! This module is entirely subservient to the GDB server. It has no SystemC

//! This module is entirely subservient to the GDB server. It has no SystemC

//! processes of its own. It provides services via calls to its API.

//! processes of its own. It provides services via calls to its API.

//! @param[in] name             Name of this module, passed to the parent

//! @param[in] name             Name of this module, passed to the parent

//!                             constructor. 

//!                             constructor. 

//! @param[in] _tapActionQueue  Pointer to fifo of actions to be performed by

//! @param[in] _tapActionQueue  Pointer to fifo of actions to be performed by

//!                             the JTAG interface

//!                             the JTAG interface

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

  sc_module (name),

  sc_module (name),

  tapActionQueue (_tapActionQueue),

  tapActionQueue (_tapActionQueue),

{

{

#ifdef NOCACHE

#ifdef NOCACHE

  npcCacheIsValid = false;              // Always cache NPC

  npcCacheIsValid = false;              // Always cache NPC

#else

#else

  sprCache = new SprCache ();

  sprCache = new SprCache ();

  memCache = new MemCache ();

  memCache = new MemCache ();

#endif

#endif

}       // DebugUnitSC ()

}       // DebugUnitSC ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Destructor

//! Destructor

//! Free up data structures

//! Free up data structures

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

  delete  sprCache;

  delete  sprCache;

#endif

#endif

}       // ~DebugUnitSC

}       // ~DebugUnitSC

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Reset the Debug Unit

//! Reset the Debug Unit

//! This is just a reset of the JTAG. It is quite possible to reset the debug

//! This is just a reset of the JTAG. It is quite possible to reset the debug

//! unit without resetting the whole target.

//! unit without resetting the whole target.

  delete resetAction;

  delete resetAction;

  delete done;

  delete done;

}       // resetDebugUnit ()

}       // resetDebugUnit ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Reset the processor

//! Reset the processor

//! Read the RISCOP register, OR in the reset bit and write it back.

//! Read the RISCOP register, OR in the reset bit and write it back.

//! After reset, the processor is known to be unstalled.

//! After reset, the processor is known to be unstalled.

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  writeRiscop (readRiscop () | RISCOP_RESET);

  writeRiscop (readRiscop () | RISCOP_RESET);

  stallState = UNKNOWN;

  stallState = UNKNOWN;

}       // reset ()

}       // reset ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Stall the processor

//! Stall the processor

//! Read the RISCOP register, OR in the stall bit and write it back.

//! Read the RISCOP register, OR in the stall bit and write it back.

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  writeRiscop (/*readRiscop () |*/ RISCOP_STALL);

  writeRiscop (/*readRiscop () |*/ RISCOP_STALL);

  stallState = STALLED;

  stallState = STALLED;

}       // stall ()

}       // stall ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Unstall the processor

//! Unstall the processor

//! Read the RISCOP register, AND out the stall bit and write it back. After

//! Read the RISCOP register, AND out the stall bit and write it back. After

//! this the NPC cache will be invalid.

//! this the NPC cache will be invalid.

//! @note Don't be tempted to read back for confirmation. Single stepping

//! @note Don't be tempted to read back for confirmation. Single stepping

//!       will already have stalled the processor again!

//!       will already have stalled the processor again!

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  writeRiscop (/*readRiscop () & ~RISCOP_STALL*/ 0);

  writeRiscop (/*readRiscop () & ~RISCOP_STALL*/ 0);

  stallState  = UNKNOWN;

  stallState  = UNKNOWN;

#ifdef NOCACHE

#ifdef NOCACHE

  memCache->clear ();

  memCache->clear ();

#endif

#endif

}       // unstall ()

}       // unstall ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Report if the processor is stalled.

//! Report if the processor is stalled.

//! A stalled processor cannot spontaneously "unstall", so if the stallState

//! A stalled processor cannot spontaneously "unstall", so if the stallState

//! flag is STALLED, that value is returned. Otherwise the target is

//! flag is STALLED, that value is returned. Otherwise the target is

//! interrogated to determine the status.

//! interrogated to determine the status.

//! @return  TRUE if the processor is known to be stalled

//! @return  TRUE if the processor is known to be stalled

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

    {

    {

      return  true;

      return  true;

    }

    }

  uint32_t  riscop = readRiscop ();

  uint32_t  riscop = readRiscop ();

  /* For some reason the reset bit is skipped over somewhere, so we should

  /* For some reason the reset bit is skipped over somewhere, so we should

  return  STALLED == stallState;

  return  STALLED == stallState;

}       // isStalled ()

}       // isStalled ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Read the value of an OpenRISC 1000 Special Purpose Register

//! Read the value of an OpenRISC 1000 Special Purpose Register

//! First see if we have the value in the cache, and if so return

//! First see if we have the value in the cache, and if so return

//! it. Otherwise, select the RISC_DEBUG scan chain and read from JTAG,

//! it. Otherwise, select the RISC_DEBUG scan chain and read from JTAG,

//! @param[in]  sprNum  The SPR to read

//! @param[in]  sprNum  The SPR to read

//! @return  The value of the SPR

//! @return  The value of the SPR

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  uint32_t  cachedValue;

  uint32_t  cachedValue;

#ifdef NOCACHE

#ifdef NOCACHE

  // Always check NPC cache

  // Always check NPC cache

      return  npcCachedValue;

      return  npcCachedValue;

    }

    }

#else

#else

  // Use any cached value if we are stalled.

  // Use any cached value if we are stalled.

      return  cachedValue;              // Already there, no more to do

      return  cachedValue;              // Already there, no more to do

    }

    }

#endif

#endif

  // Read the value

  // Read the value

  selectDebugModule (OR1K_SC_CPU0);

  selectDebugModule (OR1K_SC_CPU0);

  cachedValue = readJtagReg (sprNum);

  cachedValue = readJtagReg (sprNum);

#ifdef NOCACHE

#ifdef NOCACHE

  // Always update the NPC cache

  // Always update the NPC cache

      npcCachedValue  = cachedValue;

      npcCachedValue  = cachedValue;

      npcCacheIsValid = true;

      npcCacheIsValid = true;

    }

    }

#else

#else

  // Update the cache if we are stalled

  // Update the cache if we are stalled

      sprCache->write (sprNum, cachedValue, sprNum == SPR_NPC);

      sprCache->write (sprNum, cachedValue, sprNum == SPR_NPC);

    }

    }

#endif

#endif

  return  cachedValue;

  return  cachedValue;

}       // readSpr ()

}       // readSpr ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Write the value of an OpenRISC 1000 Special Purpose Register

//! Write the value of an OpenRISC 1000 Special Purpose Register

//! First look to see if we are stalled and the value is cached. If the value

//! First look to see if we are stalled and the value is cached. If the value

//! has not changed, then we need to no more. Otherwise cache the value prior

//! has not changed, then we need to no more. Otherwise cache the value prior

//! Select the RISC_DEBUG scan chain and write to JTAG

//! Select the RISC_DEBUG scan chain and write to JTAG

//! @param[in] sprNum  The SPR to write

//! @param[in] sprNum  The SPR to write

//! @param[in] value   The value to write

//! @param[in] value   The value to write

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

#ifdef NOCACHE

#ifdef NOCACHE

  // Always cache the NPC

  // Always cache the NPC

      // Have we already cached this NPC value?

      // Have we already cached this NPC value?

          return;

          return;

          npcCachedValue  = value;

          npcCachedValue  = value;

          npcCacheIsValid = true;

          npcCacheIsValid = true;

        }

        }

    }

    }

#else

#else

      // Have we already cached this value?

      // Have we already cached this value?

      uint32_t  cachedValue;

      uint32_t  cachedValue;

      if (sprCache->read (sprNum, cachedValue) &&

      if (sprCache->read (sprNum, cachedValue) &&

          return;                               // Already there, no more to do

          return;                               // Already there, no more to do

          sprCache->write (sprNum, value, sprNum == SPR_NPC);

          sprCache->write (sprNum, value, sprNum == SPR_NPC);

        }

        }

    }

    }

#endif

#endif

  selectDebugModule (OR1K_SC_CPU0);

  selectDebugModule (OR1K_SC_CPU0);

  writeJtagReg (sprNum, value);

  writeJtagReg (sprNum, value);

}       // writeSpr ()

}       // writeSpr ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! AND the contents of an SPR with a value

//! AND the contents of an SPR with a value

//! A convenience combination of read and write

//! A convenience combination of read and write

//! @param[in] sprNum  The SPR to write

//! @param[in] sprNum  The SPR to write

//! @param[in] value   The value to AND into the register

//! @param[in] value   The value to AND into the register

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  writeSpr (sprNum, readSpr (sprNum) & value);

  writeSpr (sprNum, readSpr (sprNum) & value);

}       // andSpr ()

}       // andSpr ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! OR the contents of an SPR with a value

//! OR the contents of an SPR with a value

//! A convenience combination of read and write

//! A convenience combination of read and write

//! @param[in] sprNum  The SPR to write

//! @param[in] sprNum  The SPR to write

//! @param[in] value   The value to OR into the register

//! @param[in] value   The value to OR into the register

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  writeSpr (sprNum, readSpr (sprNum) | value);

  writeSpr (sprNum, readSpr (sprNum) | value);

}       // orSpr ()

}       // orSpr ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Read a 32-bit word from the OpenRISC 1000 memory

//! Read a 32-bit word from the OpenRISC 1000 memory

//! Select the WISHBONE scan chain, then write the register. The data is in

//! Select the WISHBONE scan chain, then write the register. The data is in

//! model endianness and passed on without modification.

//! model endianness and passed on without modification.

//! @param[in] addr  The address to read from

//! @param[in] addr  The address to read from

//! @return  The 32-bit value read

//! @return  The 32-bit value read

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  uint32_t  cachedValue;

  uint32_t  cachedValue;

#ifndef NOCACHE

#ifndef NOCACHE

  // Use any cached value if we are stalled.

  // Use any cached value if we are stalled.

      return  cachedValue;              // Already there, no more to do

      return  cachedValue;              // Already there, no more to do

    }

    }

#endif

#endif

  // Read the value

  // Read the value

  selectDebugModule (OR1K_SC_WISHBONE);

  selectDebugModule (OR1K_SC_WISHBONE);

  cachedValue = readJtagReg (addr);

  cachedValue = readJtagReg (addr);

#ifndef NOCACHE

#ifndef NOCACHE

  // Update the cache if we are stalled

  // Update the cache if we are stalled

      memCache->write (addr, cachedValue);

      memCache->write (addr, cachedValue);

    }

    }

#endif

#endif

  return  cachedValue;

  return  cachedValue;

}       // readMem32 ()

}       // readMem32 ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Write a 32-bit word to the OpenRISC 1000 memory

//! Write a 32-bit word to the OpenRISC 1000 memory

//! Select the WISHBONE scan chain, then write the register. The data is in

//! Select the WISHBONE scan chain, then write the register. The data is in

//! model endianness and passed on without modification.

//! model endianness and passed on without modification.

//! @param[in] value  The 32-bit value to write

//! @param[in] value  The 32-bit value to write

//! @return  True if the write was successful. For now all writes are

//! @return  True if the write was successful. For now all writes are

//           successful.

//           successful.

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

#ifndef NOCACHE

#ifndef NOCACHE

      // Have we already cached this value?

      // Have we already cached this value?

      uint32_t  cachedValue;

      uint32_t  cachedValue;

          return  true;                         // Already there, no more to do

          return  true;                         // Already there, no more to do

          memCache->write (addr, value);        // Write for the future

          memCache->write (addr, value);        // Write for the future

        }

        }

    }

    }

#endif

#endif

  return  true;

  return  true;

}       // writeMem32 ()

}       // writeMem32 ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Read a byte from the OpenRISC 1000 main memory

//! Read a byte from the OpenRISC 1000 main memory

//! All we can get are 32-bits words, so we have to unpick the value.

//! All we can get are 32-bits words, so we have to unpick the value.

//! @note Read bytes from memory mapped devices at your peril!

//! @note Read bytes from memory mapped devices at your peril!

//! @param[in] addr  The address to read from

//! @param[in] addr  The address to read from

//! @return  The byte read

//! @return  The byte read

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  uint32_t  word   = Utils::ttohl (readMem32 (addr & 0xfffffffc));

  uint32_t  word   = Utils::ttohl (readMem32 (addr & 0xfffffffc));

  uint8_t  *bytes  = (uint8_t *)(&word);

  uint8_t  *bytes  = (uint8_t *)(&word);

  int       offset = addr & 0x3;

  int       offset = addr & 0x3;

  return  bytes[offset];

  return  bytes[offset];

}       // readMem8 ()

}       // readMem8 ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Write a byte to the OpenRISC 1000 main memory

//! Write a byte to the OpenRISC 1000 main memory

//! All we can get are 32-bits words, so we have to read the current value and

//! All we can get are 32-bits words, so we have to read the current value and

//! construct the new value to write back.

//! construct the new value to write back.

//! @param[in] value  The byte to write

//! @param[in] value  The byte to write

//! @return  True if the write was successful. For now all writes are

//! @return  True if the write was successful. For now all writes are

//           successful.

//           successful.

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  uint32_t  currWord  = Utils::ttohl (readMem32 (addr & 0xfffffffc));

  uint32_t  currWord  = Utils::ttohl (readMem32 (addr & 0xfffffffc));

  uint8_t  *currBytes = (uint8_t *)(&currWord);

  uint8_t  *currBytes = (uint8_t *)(&currWord);

  int       offset    = addr & 0x3;

  int       offset    = addr & 0x3;

  return  writeMem32 (addr & 0xfffffffc, Utils::htotl (currWord));

  return  writeMem32 (addr & 0xfffffffc, Utils::htotl (currWord));

}       // writeMem8 ()

}       // writeMem8 ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Get the debug interface CPU0 control register value

//! Get the debug interface CPU0 control register value

//! @return  The value in the RISCOP register

//! @return  The value in the RISCOP register

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  selectDebugModule (OR1K_SC_CPU0);

  selectDebugModule (OR1K_SC_CPU0);

  int  drLen;                   // Size of the data register

  int  drLen;                   // Size of the data register

  // Allocate a SystemC completion event

  // Allocate a SystemC completion event

  sc_event *done  = new sc_event();

  sc_event *done  = new sc_event();

  // Loop until status is OK and CRCs match.

  // Loop until status is OK and CRCs match.

      tapActionQueue->write (dRScan);

      tapActionQueue->write (dRScan);

      wait (*done);

      wait (*done);

      dRScan->getDRegOut (dRegOut);

      dRScan->getDRegOut (dRegOut);

      delete dRScan;

      delete dRScan;

      status_ret = unpackBits (dRegOut,1+4+32+52,4);

      status_ret = unpackBits (dRegOut,1+4+32+52,4);

      calc_recv_crc = crc32(dRegOut,52+4,1+4+32);

      calc_recv_crc = crc32(dRegOut,52+4,1+4+32);

    }

    }

  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));

  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));

  // All done

  // All done

  uint32_t  res = BITREV(unpackBits (dRegOut, (1+4+32),2),2);

  uint32_t  res = BITREV(unpackBits (dRegOut, (1+4+32),2),2);

  delete [] dRegOut;

  delete [] dRegOut;

  delete  done;

  delete  done;

  return  res;

  return  res;

}       // readRiscop ()

}       // readRiscop ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Set the RISCOP control register

//! Set the RISCOP control register

//! Convenience function. Select the REGISTER scan chain, write the new value.

//! Convenience function. Select the REGISTER scan chain, write the new value.

//! @param[in] value  The value to write into the RISCOP register

//! @param[in] value  The value to write into the RISCOP register

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  selectDebugModule (OR1K_SC_CPU0);

  selectDebugModule (OR1K_SC_CPU0);

  int  drLen;                   // Size of the data register

  int  drLen;                   // Size of the data register

  // Allocate a SystemC completion event

  // Allocate a SystemC completion event

  sc_event *done  = new sc_event();

  sc_event *done  = new sc_event();

  // Loop until status is OK and CRCs match.

  // Loop until status is OK and CRCs match.

      tapActionQueue->write (dRScan);

      tapActionQueue->write (dRScan);

      wait (*done);

      wait (*done);

      dRScan->getDRegOut (dRegOut);

      dRScan->getDRegOut (dRegOut);

      delete dRScan;

      delete dRScan;

      status_ret = unpackBits (dRegOut,1+4+32+52,4);

      status_ret = unpackBits (dRegOut,1+4+32+52,4);

      calc_recv_crc = crc32(dRegOut,4,1+4+52+32);

      calc_recv_crc = crc32(dRegOut,4,1+4+52+32);

    }

    }

  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));

  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));

  delete [] dRegIn;

  delete [] dRegIn;

  delete [] dRegOut;

  delete [] dRegOut;

  delete  done;

  delete  done;

}       // writeRiscop ()

}       // writeRiscop ()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Select a module attached to the debug module

//! Select a module attached to the debug module

//! @note Must be called from a SystemC thread, because of the use of wait()

//! @note Must be called from a SystemC thread, because of the use of wait()

//! @param[in] chain  The desired module

//! @param[in] chain  The desired module

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

      return;

      return;

      currentScanChain = module;

      currentScanChain = module;

    }

    }

  sc_event        *done = new sc_event();

  sc_event        *done = new sc_event();

  TapActionIRScan *iRScan;

  TapActionIRScan *iRScan;

  uint64_t *dRegIn  = new uint64_t [(DUSEL_DR_LEN + 63) / 64];

  uint64_t *dRegIn  = new uint64_t [(DUSEL_DR_LEN + 63) / 64];

  uint64_t *dRegOut = new uint64_t [(DUSEL_DR_LEN + 63) / 64];

  uint64_t *dRegOut = new uint64_t [(DUSEL_DR_LEN + 63) / 64];

  clearBits (dRegIn, DUSEL_DR_LEN);

  clearBits (dRegIn, DUSEL_DR_LEN);

  packBits (dRegIn, DUSEL_SEL_OFF, DUSEL_SEL_LEN, 0x1);

  packBits (dRegIn, DUSEL_SEL_OFF, DUSEL_SEL_LEN, 0x1);

  uint32_t crc32_send = crc32 (dRegIn, DUSEL_CRC_OFF, 0);

  uint32_t crc32_send = crc32 (dRegIn, DUSEL_CRC_OFF, 0);

  uint32_t calc_recv_crc = 0, recv_crc, status_ret;

  uint32_t calc_recv_crc = 0, recv_crc, status_ret;

  // Loop until status is OK and CRCs match.

  // Loop until status is OK and CRCs match.

      tapActionQueue->write (dRScan);

      tapActionQueue->write (dRScan);

      wait (*done);

      wait (*done);

      dRScan->getDRegOut (dRegOut);

      dRScan->getDRegOut (dRegOut);

      delete dRScan;

      delete dRScan;

    }

    }

  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));

  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));

  delete [] dRegIn;

  delete [] dRegIn;

  delete [] dRegOut;

  delete [] dRegOut;

  delete done;

  delete done;

}       // selectDebugModule()

}       // selectDebugModule()

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//! Read a 32-bit value via the debug interface

//! Read a 32-bit value via the debug interface

//! @note Must be called from a SystemC thread, because of the use of wait()

//! @note Must be called from a SystemC thread, because of the use of wait()

//! @param[in] addr  The address of the register

//! @param[in] addr  The address of the register

//! @return  The register value read

//! @return  The register value read

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

{

{

  int  drLen;                   // Size of the data register

  int  drLen;                   // Size of the data register

  uint32_t calc_recv_crc = 0, recv_crc, status_ret;

  uint32_t calc_recv_crc = 0, recv_crc, status_ret;

  // Allocate a SystemC completion event

  // Allocate a SystemC completion event

  sc_event *done  = new sc_event();

  sc_event *done  = new sc_event();

  // Loop until status is OK and CRCs match.

  // Loop until status is OK and CRCs match.

      tapActionQueue->write (dRScan);

      tapActionQueue->write (dRScan);

      wait (*done);

      wait (*done);

      dRScan->getDRegOut (dRegOut);

      dRScan->getDRegOut (dRegOut);

      delete dRScan;

      delete dRScan;

      status_ret = unpackBits (dRegOut,1+4+4+32+16+32,4);

      status_ret = unpackBits (dRegOut,1+4+4+32+16+32,4);

      calc_recv_crc = crc32(dRegOut,4,1+4+4+32+16+32);

      calc_recv_crc = crc32(dRegOut,4,1+4+4+32+16+32);

    }

    }

  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));

  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));

  clearBits (dRegIn, drLen);

  clearBits (dRegIn, drLen);

  packBits (dRegIn, 0, 1, 0);

  packBits (dRegIn, 0, 1, 0);

  crc32_send = crc32 (dRegIn,1+4,0);

  crc32_send = crc32 (dRegIn,1+4,0);

  packBits (dRegIn, 1+4, 32, BITREV(crc32_send,32)); // CRC

  packBits (dRegIn, 1+4, 32, BITREV(crc32_send,32)); // CRC

  uint32_t  result;

  uint32_t  result;

  // Loop until status is OK and CRCs match.

  // Loop until status is OK and CRCs match.

      tapActionQueue->write (dRScan);

      tapActionQueue->write (dRScan);

      wait (*done);

      wait (*done);

      dRScan->getDRegOut (dRegOut);

      dRScan->getDRegOut (dRegOut);

      delete dRScan;

      delete dRScan;