OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [Or1200MonitorSC.cpp] - Diff between revs 353 and 354

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 353 Rev 354
Line 186... Line 186...
                      sscanf( argv[i+1], "0x%x", &memdump_end);
                      sscanf( argv[i+1], "0x%x", &memdump_end);
                      i++;
                      i++;
                    }
                    }
                }
                }
            }
            }
          else if ((strcmp(argv[i], "-u")==0) ||
          /*
                   (strcmp(argv[i], "--bus-log")==0))
          else if ((strcmp(argv[i], "-u")==0) ||
            {
                   (strcmp(argv[i], "--bus-log")==0))
              bus_trans_log_enabled = true;
            {
              if (i+1 < argc)
              bus_trans_log_enabled = true;
                if(argv[i+1][0] != '-')
              if (i+1 < argc)
                  {
                if(argv[i+1][0] != '-')
                    bus_trans_log_file = (argv[i+1]);
                  {
                    bus_trans_log_name_provided = true;
                    bus_trans_log_file = (argv[i+1]);
                  }
                    bus_trans_log_name_provided = true;
 
                  }
 
 
              if (!bus_trans_log_name_provided)
              if (!bus_trans_log_name_provided)
                bus_trans_log_file = bus_trans_default_log_name;
                bus_trans_log_file = bus_trans_default_log_name;
 
 
              // check for a log start delay
              // check for a log start delay
              if (i+2 < argc)
              if (i+2 < argc)
                if(argv[i+2][0] != '-')
                if(argv[i+2][0] != '-')
                  {
                  {
                    // We have a bus transaction log start delay
                    // We have a bus transaction log start delay
                    bus_trans_log_start_delay_enable = true;
                    bus_trans_log_start_delay_enable = true;
                    int time_val = atoi(argv[i+2]);
                    int time_val = atoi(argv[i+2]);
                    sc_time log_start_time(time_val,SC_NS);
                    sc_time log_start_time(time_val,SC_NS);
                    bus_trans_log_start_delay = log_start_time;
                    bus_trans_log_start_delay = log_start_time;
                  }
                  }
            }
            }
 
          */
        }
        }
    }
    }
 
 
 
 
  if (!rsp_server_enabled)
  if (!rsp_server_enabled)
Line 373... Line 375...
  printf("  -b, --binlog <file>\tGenerate binary format execution log (faster, smaller)\n");
  printf("  -b, --binlog <file>\tGenerate binary format execution log (faster, smaller)\n");
 
 
  printf("  -q, --quiet\t\tDisable the performance summary at end of simulation\n");
  printf("  -q, --quiet\t\tDisable the performance summary at end of simulation\n");
  printf("  -m, --memdump <file> <0xstartaddr> <0xendaddr>\n\t\t\tDump data between <0xstartaddr> and <0xendaddr> from\n\t\t\tthe system's RAM to <file> in binary format on exit\n");
  printf("  -m, --memdump <file> <0xstartaddr> <0xendaddr>\n\t\t\tDump data between <0xstartaddr> and <0xendaddr> from\n\t\t\tthe system's RAM to <file> in binary format on exit\n");
  printf("  -c, --crash-monitor\tDetect when the processor has crashed and exit\n");
  printf("  -c, --crash-monitor\tDetect when the processor has crashed and exit\n");
  printf("  -u, --bus-log <file> <val>\n\t\t\tLog the wishbone bus transactions to <file>, opt. start\n\t\t\tafter <val> ns\n\n");
/*
 
  printf("  -u, --bus-log <file> <val>\n\t\t\tLog the wishbone bus transactions to <file>, opt. start\n\t\t\tafter <val> ns\n\n");
 
*/
 
 
}
}
 
 
//! Method to handle special instrutions
//! Method to handle special instrutions
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.