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Line 189... |
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} // getWbInsn ()
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} // getWbInsn ()
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//! Access the Wishbone SRAM memory
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//! Access the Wishbone SRAM memory
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//! @return The value of the memory word at addr
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//! @return The value of the 32-bit memory word at addr
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uint32_t
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uint32_t
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OrpsocAccess::get_mem (uint32_t addr)
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OrpsocAccess::get_mem32 (uint32_t addr)
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{
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{
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return (ram_wb_sc_sw->get_mem) (addr);
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return (ram_wb_sc_sw->get_mem) (addr/4);
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} // get_mem32 ()
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//! Access a byte from the Wishbone SRAM memory
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//! @return The value of the memory byte at addr
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uint8_t
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OrpsocAccess::get_mem8 (uint32_t addr)
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{
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uint32_t word;
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static uint32_t cached_word;
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static uint32_t cached_word_addr = 0xffffffff;
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int sel = addr & 0x3; // Remember which byte we want
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addr = addr / 4;
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if (addr != cached_word_addr)
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{
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cached_word_addr = addr;
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// Convert address to word number here
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word = (ram_wb_sc_sw->get_mem) (addr);
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cached_word = word;
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}
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else
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word = cached_word;
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switch(sel)
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{
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/* Big endian word expected */
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case 0:
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return ((word >> 24) & 0xff);
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break;
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case 1:
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return ((word >> 16) & 0xff);
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break;
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case 2:
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return ((word >> 8) & 0xff);
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break;
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case 3:
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return ((word >> 0) & 0xff);
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break;
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default:
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return 0;
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}
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} // get_mem8 ()
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} // get_mem ()
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//! Write value to the Wishbone SRAM memory
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//! Write value to the Wishbone SRAM memory
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void
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void
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OrpsocAccess::set_mem (uint32_t addr, uint32_t data)
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OrpsocAccess::set_mem32 (uint32_t addr, uint32_t data)
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{
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{
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(ram_wb_sc_sw->set_mem) (addr, data);
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(ram_wb_sc_sw->set_mem) (addr/4, data);
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} // set_mem ()
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} // set_mem32 ()
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//! Trigger the $readmemh() system call
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//! Trigger the $readmemh() system call
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void
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void
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OrpsocAccess::do_ram_readmemh (void)
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OrpsocAccess::do_ram_readmemh (void)
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