Line 46... |
Line 46... |
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#include "Vorpsoc_top.h"
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#include "Vorpsoc_top.h"
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#include "OrpsocAccess.h"
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#include "OrpsocAccess.h"
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#include "MemoryLoad.h"
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#include "MemoryLoad.h"
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#include <SpTraceVcdC.h>
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#include <verilated_vcd_c.h>
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#include "ResetSC.h"
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#include "ResetSC.h"
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#include "Or1200MonitorSC.h"
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#include "Or1200MonitorSC.h"
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#include "GdbServerSC.h"
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#include "GdbServerSC.h"
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#include "UartSC.h"
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#include "UartSC.h"
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Line 102... |
Line 102... |
bool dump_start_delay_set = false, dump_stop_set = false;
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bool dump_start_delay_set = false, dump_stop_set = false;
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bool dumping_now = false;
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bool dumping_now = false;
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int dump_depth = 99; // Default dump depth
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int dump_depth = 99; // Default dump depth
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sc_time dump_start,dump_stop, finish_time;
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sc_time dump_start,dump_stop, finish_time;
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bool finish_time_set = false; // By default we will let the simulation finish naturally
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bool finish_time_set = false; // By default we will let the simulation finish naturally
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SpTraceVcdCFile *spTraceFile;
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VerilatedVcdC *verilatorVCDFile;
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/*int*/double time_val;
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/*int*/double time_val;
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bool vcd_file_name_given = false;
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bool vcd_file_name_given = false;
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bool rsp_server_enabled = false;
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bool rsp_server_enabled = false;
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Line 332... |
Line 332... |
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printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
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printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
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// Establish a new trace with its correct time resolution, and trace to
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// Establish a new trace with its correct time resolution, and trace to
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// great depth.
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// great depth.
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spTraceFile = new SpTraceVcdCFile ();
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verilatorVCDFile = new VerilatedVcdC ();
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//spTraceFile->spTrace()->set_time_resolution (sc_get_time_resolution());
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//verilatorVCDFile->verilated()->set_time_resolution (sc_get_time_resolution());
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//setSpTimeResolution (sc_get_time_resolution ());
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//setSpTimeResolution (sc_get_time_resolution ());
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//traceTarget->trace (spTraceFile, 99);
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//traceTarget->trace (verilatorVCDFile, 99);
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orpsoc->trace (spTraceFile, dump_depth);
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orpsoc->trace (verilatorVCDFile, dump_depth);
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if (dumping_now)
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if (dumping_now)
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{
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{
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spTraceFile->open (vcdDumpFile.c_str());
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verilatorVCDFile->open (vcdDumpFile.c_str());
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}
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}
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}
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}
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//printf("* Beginning test\n");
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//printf("* Beginning test\n");
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Line 386... |
Line 386... |
if (dump_start_delay_set)
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if (dump_start_delay_set)
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{
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{
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// Run the sim until we want to dump
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// Run the sim until we want to dump
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sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
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sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
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// Open the trace file
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// Open the trace file
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spTraceFile->open (vcdDumpFile.c_str());
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verilatorVCDFile->open (vcdDumpFile.c_str());
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dumping_now = 1;
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dumping_now = 1;
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}
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}
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if (dumping_now)
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if (dumping_now)
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{
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{
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Line 400... |
Line 400... |
{
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{
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if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
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if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
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sc_start (1,TIMESCALE_UNIT); // Step the sim
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sc_start (1,TIMESCALE_UNIT); // Step the sim
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else
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else
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{
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{
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spTraceFile->close();
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verilatorVCDFile->close();
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break;
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break;
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}
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}
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spTraceFile->dump (sc_time_stamp().to_double());
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verilatorVCDFile->dump (sc_time_stamp().to_double());
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if (dump_stop_set)
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if (dump_stop_set)
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{
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{
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if (sc_time_stamp() >= dump_stop)
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if (sc_time_stamp() >= dump_stop)
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{
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{
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// Close dump file
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// Close dump file
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spTraceFile->close();
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verilatorVCDFile->close();
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// Now continue on again until the end
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// Now continue on again until the end
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if (!finish_time_set)
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if (!finish_time_set)
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sc_start();
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sc_start();
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else
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else
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{
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{
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Line 439... |
Line 439... |
if (sc_time_stamp() >= finish_time)
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if (sc_time_stamp() >= finish_time)
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{
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{
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// Officially stop the sim
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// Officially stop the sim
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sc_stop();
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sc_stop();
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// Close dump file
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// Close dump file
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spTraceFile->close();
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verilatorVCDFile->close();
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// Do memdump if enabled
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// Do memdump if enabled
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monitor->memdump();
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monitor->memdump();
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// Print performance summary
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// Print performance summary
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monitor->perfSummary();
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monitor->perfSummary();
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break;
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break;
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