| Line 67... |
Line 67... |
sc_clock clk ("clk", clkPeriod);
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sc_clock clk ("clk", clkPeriod);
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sc_clock jtag_tck ("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
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sc_clock jtag_tck ("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
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sc_signal<bool> rst;
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sc_signal<bool> rst;
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sc_signal<bool> rstn;
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sc_signal<bool> rstn;
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sc_signal<bool> rst_o;
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sc_signal<bool> jtag_tdi; // JTAG interface
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sc_signal<bool> jtag_tdi; // JTAG interface
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sc_signal<bool> jtag_tdo;
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sc_signal<bool> jtag_tdo;
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sc_signal<bool> jtag_tms;
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sc_signal<bool> jtag_tms;
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sc_signal<bool> jtag_trst;
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sc_signal<bool> jtag_trst;
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sc_signal<bool> uart_rx; // External UART
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sc_signal<bool> uart_rx; // External UART
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sc_signal<bool> uart_tx;
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sc_signal<bool> uart_tx;
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sc_signal<bool> spi_sd_sclk; // SD Card Memory SPI
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sc_signal<bool> spi_sd_ss;
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sc_signal<bool> spi_sd_miso;
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sc_signal<bool> spi_sd_mosi;
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sc_signal<uint32_t> gpio_a; // GPIO bus - output only in verilator sims
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sc_signal<bool> spi1_mosi;
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sc_signal<bool> spi1_miso;
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sc_signal<bool> spi1_ss;
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sc_signal<bool> spi1_sclk;
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SIM_RUNNING = 0;
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SIM_RUNNING = 0;
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// Setup the name of the VCD dump file
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// Setup the name of the VCD dump file
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bool VCD_enabled = false;
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bool VCD_enabled = false;
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string dumpNameDefault("vlt-dump.vcd");
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string dumpNameDefault("vlt-dump.vcd");
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| Line 272... |
Line 259... |
else
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else
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gdbServer = NULL;
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gdbServer = NULL;
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// Connect up ORPSoC
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// Connect up ORPSoC
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orpsoc->clk_pad_i (clk);
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orpsoc->clk_pad_i (clk);
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orpsoc->rst_pad_i (rstn);
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orpsoc->rst_n_pad_i (rstn);
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orpsoc->rst_pad_o (rst_o);
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orpsoc->dbg_tck_pad_i (jtag_tck); // JTAG interface
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orpsoc->tck_pad_i (jtag_tck); // JTAG interface
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orpsoc->dbg_tdi_pad_i (jtag_tdi);
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orpsoc->tdi_pad_i (jtag_tdi);
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orpsoc->dbg_tms_pad_i (jtag_tms);
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orpsoc->tms_pad_i (jtag_tms);
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orpsoc->dbg_tdo_pad_o (jtag_tdo);
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orpsoc->tdo_pad_o (jtag_tdo);
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orpsoc->uart0_srx_pad_i (uart_rx); // External UART
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orpsoc->uart0_srx_pad_i (uart_rx); // External UART
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orpsoc->uart0_stx_pad_o (uart_tx);
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orpsoc->uart0_stx_pad_o (uart_tx);
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orpsoc->spi_sd_sclk_pad_o (spi_sd_sclk); // SD Card Memory SPI
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orpsoc->spi_sd_ss_pad_o (spi_sd_ss);
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orpsoc->spi_sd_miso_pad_i (spi_sd_miso);
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orpsoc->spi_sd_mosi_pad_o (spi_sd_mosi);
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orpsoc->spi1_mosi_pad_o (spi1_mosi);
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orpsoc->spi1_miso_pad_i (spi1_miso);
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orpsoc->spi1_ss_pad_o (spi1_ss);
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orpsoc->spi1_sclk_pad_o (spi1_sclk);
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orpsoc->gpio_a_pad_io (gpio_a); // GPIO bus - output only in
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// verilator sims
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// Connect up the SystemC modules
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// Connect up the SystemC modules
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reset->clk (clk); // Reset
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reset->clk (clk); // Reset
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reset->rst (rst);
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reset->rst (rst);
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reset->rstn (rstn);
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reset->rstn (rstn);
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| Line 319... |
Line 291... |
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// Tie off signals
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// Tie off signals
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jtag_tdi = 1; // Tie off the JTAG inputs
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jtag_tdi = 1; // Tie off the JTAG inputs
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jtag_tms = 1;
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jtag_tms = 1;
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spi_sd_miso = 0; // Tie off master-in/slave-out of SD SPI bus
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spi1_miso = 0;
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if (VCD_enabled)
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if (VCD_enabled)
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{
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{
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Verilated::traceEverOn (true);
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Verilated::traceEverOn (true);
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printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
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printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
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