| Line 8... |
Line 8... |
//// To Do: ////
|
//// To Do: ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Jeremy Bennett jeremy.bennett@embecosm.com ////
|
//// - Jeremy Bennett jeremy.bennett@embecosm.com ////
|
//// - Julius Baxter jb@orsoc.se ////
|
//// - Julius Baxter julius@opencores.org ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| Line 40... |
Line 40... |
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
#include "OrpsocMain.h"
|
#include "OrpsocMain.h"
|
|
|
// TODO - copy orpsoc-defines.h and or1200-defines.h somewhere this can see
|
|
// them and include/exclude RSP stuff. For now is defined
|
|
|
|
|
|
#include "Vorpsoc_top.h"
|
#include "Vorpsoc_top.h"
|
#include "OrpsocAccess.h"
|
#include "OrpsocAccess.h"
|
#include "MemoryLoad.h"
|
#include "MemoryLoad.h"
|
|
|
#include <verilated_vcd_c.h>
|
#include <verilated_vcd_c.h>
|
|
|
#include "ResetSC.h"
|
#include "ResetSC.h"
|
#include "Or1200MonitorSC.h"
|
#include "Or1200MonitorSC.h"
|
|
|
|
|
// Include Verilog ORPSoC defines file, converted to C include format to be
|
// Include Verilog ORPSoC defines file, converted to C include format to be
|
// able to detect if the debug unit is to be built in or not.
|
// able to detect if the debug unit is to be built in or not.
|
#include "orpsoc-defines.h"
|
#include "orpsoc-defines.h"
|
|
|
|
|
#ifdef JTAG_DEBUG
|
#ifdef JTAG_DEBUG
|
# include "GdbServerSC.h"
|
# include "GdbServerSC.h"
|
# include "JtagSC_includes.h"
|
# include "JtagSC_includes.h"
|
#endif
|
#endif
|
|
|
#ifdef UART0
|
#ifdef UART0
|
# include "UartSC.h"
|
# include "UartSC.h"
|
#endif
|
#endif
|
|
|
int SIM_RUNNING;
|
/* Global quiet variable */
|
int sc_main (int argc,
|
bool gQuiet;
|
char *argv[] )
|
|
|
int gSimRunning;
|
|
|
|
int sc_main(int argc, char *argv[])
|
{
|
{
|
sc_set_time_resolution( 1, TIMESCALE_UNIT);
|
sc_set_time_resolution( 1, TIMESCALE_UNIT);
|
// CPU clock (also used as JTAG TCK) and reset (both active high and low)
|
// CPU clock (also used as JTAG TCK) and reset (both active high and low)
|
sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
|
sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
|
sc_clock clk ("clk", clkPeriod);
|
sc_clock clk ("clk", clkPeriod);
|
| Line 95... |
Line 92... |
#ifdef UART0
|
#ifdef UART0
|
sc_signal<bool> uart_rx; // External UART
|
sc_signal<bool> uart_rx; // External UART
|
sc_signal<bool> uart_tx;
|
sc_signal<bool> uart_tx;
|
#endif
|
#endif
|
|
|
SIM_RUNNING = 0;
|
gSimRunning = 0;
|
|
|
// Are we running "quiet"?
|
// Are we running "quiet"?
|
bool quiet = false;
|
gQuiet = false;
|
// Setup the name of the VCD dump file
|
// Setup the name of the VCD dump file
|
bool VCD_enabled = false;
|
bool VCD_enabled = false;
|
string dumpNameDefault("vlt-dump.vcd");
|
string dumpNameDefault("vlt-dump.vcd");
|
string testNameString;
|
string testNameString;
|
string vcdDumpFile;
|
string vcdDumpFile;
|
| Line 173... |
Line 170... |
// Parse command line options
|
// Parse command line options
|
// Default is for VCD generation OFF, only turned on if specified on command
|
// Default is for VCD generation OFF, only turned on if specified on command
|
// line
|
// line
|
|
|
// Search through the command line parameters for options
|
// Search through the command line parameters for options
|
if (argc > 1)
|
if (argc > 1) {
|
{
|
for (int i = 1; i < argc; i++) {
|
for(int i=1; i<argc; i++)
|
|
{
|
|
if ( (strcmp(argv[i], "-e")==0) ||
|
if ( (strcmp(argv[i], "-e")==0) ||
|
(strcmp(argv[i], "--endtime")==0) )
|
(strcmp(argv[i], "--endtime") == 0)) {
|
{
|
|
time_val = strtod(argv[i+1], NULL);
|
time_val = strtod(argv[i+1], NULL);
|
sc_time opt_end_time(time_val,TIMESCALE_UNIT);
|
sc_time opt_end_time(time_val,TIMESCALE_UNIT);
|
finish_time = opt_end_time;
|
finish_time = opt_end_time;
|
finish_time_set = true;
|
finish_time_set = true;
|
}
|
} else if ((strcmp(argv[i], "-q") == 0) ||
|
else if ( (strcmp(argv[i], "-f")==0) ||
|
(strcmp(argv[i], "--quiet") == 0)) {
|
(strcmp(argv[i], "--program")==0) )
|
gQuiet = true;
|
{
|
} else if ((strcmp(argv[i], "-f") == 0) ||
|
|
(strcmp(argv[i], "--program") == 0)) {
|
do_program_file_load = 1; // Enable program loading - will be
|
do_program_file_load = 1; // Enable program loading - will be
|
// done after sim init.
|
// done after sim init.
|
program_file = argv[i+1]; // Old char* style for program name
|
program_file = argv[i+1]; // Old char* style for program name
|
}
|
} else if ((strcmp(argv[i], "-d") == 0) ||
|
else if ((strcmp(argv[i], "-d")==0) ||
|
|
(strcmp(argv[i], "--vcdfile")==0) ||
|
(strcmp(argv[i], "--vcdfile")==0) ||
|
(strcmp(argv[i], "-v")==0) ||
|
(strcmp(argv[i], "-v")==0) ||
|
(strcmp(argv[i], "--vcdon")==0)
|
(strcmp(argv[i], "--vcdon")==0)
|
)
|
) {
|
{
|
|
VCD_enabled = true;
|
VCD_enabled = true;
|
dumping_now = true;
|
dumping_now = true;
|
vcdDumpFile = dumpNameDefault;
|
vcdDumpFile = dumpNameDefault;
|
if (i+1 < argc)
|
if (i+1 < argc)
|
if(argv[i+1][0] != '-')
|
if (argv[i + 1][0] != '-') {
|
{
|
|
testNameString = argv[i+1];
|
testNameString = argv[i+1];
|
vcdDumpFile = testNameString;
|
vcdDumpFile = testNameString;
|
i++;
|
i++;
|
}
|
}
|
}
|
} else if ((strcmp(argv[i], "-s") == 0) ||
|
else if ( (strcmp(argv[i], "-s")==0) ||
|
(strcmp(argv[i], "--vcdstart") == 0)) {
|
(strcmp(argv[i], "--vcdstart")==0) )
|
|
{
|
|
VCD_enabled = true;
|
VCD_enabled = true;
|
time_val = strtod(argv[i+1], NULL);
|
time_val = strtod(argv[i+1], NULL);
|
sc_time dump_start_time(time_val,TIMESCALE_UNIT);
|
sc_time dump_start_time(time_val,
|
|
TIMESCALE_UNIT);
|
dump_start = dump_start_time;
|
dump_start = dump_start_time;
|
dump_start_delay_set = true;
|
dump_start_delay_set = true;
|
dumping_now = false;
|
dumping_now = false;
|
}
|
} else if ((strcmp(argv[i], "-t") == 0) ||
|
else if ( (strcmp(argv[i], "-t")==0) ||
|
(strcmp(argv[i], "--vcdstop") == 0)) {
|
(strcmp(argv[i], "--vcdstop")==0) )
|
|
{
|
|
VCD_enabled = true;
|
VCD_enabled = true;
|
time_val = strtod(argv[i+1],NULL);
|
time_val = strtod(argv[i+1],NULL);
|
sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
|
sc_time dump_stop_time(time_val,
|
|
TIMESCALE_UNIT);
|
dump_stop = dump_stop_time;
|
dump_stop = dump_stop_time;
|
dump_stop_set = true;
|
dump_stop_set = true;
|
}
|
}
|
/*
|
|
Depth setting of VCD doesn't appear to work, I think it's only
|
|
configurable during at compile time .
|
|
*/
|
|
/* else if ( (strcmp(argv[i], "-p")==0) ||
|
|
(strcmp(argv[i], "--vcddepth")==0) )
|
|
{
|
|
dump_depth = atoi(argv[i+1]);
|
|
}*/
|
|
#ifdef JTAG_DEBUG
|
#ifdef JTAG_DEBUG
|
else if ( (strcmp(argv[i], "-r")==0) ||
|
else if ( (strcmp(argv[i], "-r")==0) ||
|
(strcmp(argv[i], "--rsp")==0) )
|
(strcmp(argv[i], "--rsp") == 0)) {
|
{
|
|
rsp_server_enabled = true;
|
rsp_server_enabled = true;
|
if (i+1 < argc) if(argv[i+1][0] != '-')
|
if (i + 1 < argc)
|
{
|
if (argv[i + 1][0] != '-') {
|
rsp_server_port = atoi(argv[i+1]);
|
rsp_server_port =
|
|
atoi(argv[i + 1]);
|
i++;
|
i++;
|
}
|
}
|
}
|
}
|
#endif
|
#endif
|
else if ((strcmp(argv[i], "-q")==0) ||
|
|
(strcmp(argv[i], "--quiet")==0))
|
|
{
|
|
quiet = true;
|
|
}
|
|
else if ( (strcmp(argv[i], "-h")==0) ||
|
else if ( (strcmp(argv[i], "-h")==0) ||
|
(strcmp(argv[i], "--help")==0) )
|
(strcmp(argv[i], "--help") == 0)) {
|
{
|
|
printf("Usage: %s [options]\n",argv[0]);
|
printf("Usage: %s [options]\n",argv[0]);
|
printf("\n ORPSoCv2 cycle accurate model\n");
|
printf("\n ORPSoCv2 cycle accurate model\n");
|
printf(" For details visit http://opencores.org/openrisc,orpsocv2\n");
|
printf
|
|
(" For details visit http://opencores.org/openrisc,orpsocv2\n");
|
printf("\n");
|
printf("\n");
|
printf("Options:\n");
|
printf("Options:\n");
|
printf(" -h, --help\t\tPrint this help message\n");
|
printf
|
printf(" -q, --quiet\t\tDisable all except UART print out\n");
|
(" -h, --help\t\tPrint this help message\n");
|
|
printf
|
|
(" -q, --quiet\t\tDisable all except UART print out\n");
|
printf("\nSimulation control:\n");
|
printf("\nSimulation control:\n");
|
printf(" -f, --program <file> \tLoad program from OR32 ELF <file>\n");
|
printf
|
printf(" -e, --endtime <val> \tStop the sim at <val> ns\n");
|
(" -f, --program <file> \tLoad program from OR32 ELF <file>\n");
|
|
printf
|
|
(" -e, --endtime <val> \tStop the sim at <val> ns\n");
|
printf("\nVCD generation:\n");
|
printf("\nVCD generation:\n");
|
printf(" -v, --vcdon\t\tEnable VCD generation\n");
|
printf
|
printf(" -d, --vcdfile <file>\tEnable and save VCD to <file>\n");
|
(" -v, --vcdon\t\tEnable VCD generation\n");
|
|
printf
|
printf(" -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");
|
(" -d, --vcdfile <file>\tEnable and save VCD to <file>\n");
|
printf(" -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");
|
|
|
printf
|
|
(" -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");
|
|
printf
|
|
(" -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");
|
#ifdef JTAG_DEBUG
|
#ifdef JTAG_DEBUG
|
printf("\nRemote debugging:\n");
|
printf("\nRemote debugging:\n");
|
printf(" -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");
|
printf
|
|
(" -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");
|
#endif
|
#endif
|
monitor->printUsage();
|
monitor->printUsage();
|
printf("\n");
|
printf("\n");
|
return 0;
|
return 0;
|
}
|
}
|
|
|
}
|
}
|
}
|
}
|
|
|
// Determine if we're going to setup a VCD dump:
|
// Determine if we're going to setup a VCD dump:
|
// Pretty much setting any related option will enable VCD dumping.
|
// Pretty much setting any related option will enable VCD dumping.
|
if (VCD_enabled)
|
if (VCD_enabled) {
|
{
|
|
|
|
cout << "* Enabling VCD trace";
|
cout << "* Enabling VCD trace";
|
|
|
if (dump_start_delay_set)
|
if (dump_start_delay_set)
|
cout << ", on at time " << dump_start.to_string();
|
cout << ", on at time " << dump_start.to_string();
|
| Line 300... |
Line 283... |
cout << ", off at time " << dump_stop.to_string();
|
cout << ", off at time " << dump_stop.to_string();
|
cout << endl;
|
cout << endl;
|
}
|
}
|
#ifdef JTAG_DEBUG
|
#ifdef JTAG_DEBUG
|
if (rsp_server_enabled)
|
if (rsp_server_enabled)
|
gdbServer = new GdbServerSC ("gdb-server", FLASH_START, FLASH_END,
|
gdbServer =
|
|
new GdbServerSC("gdb-server", FLASH_START, FLASH_END,
|
rsp_server_port, jtag->tapActionQueue);
|
rsp_server_port, jtag->tapActionQueue);
|
else
|
else
|
gdbServer = NULL;
|
gdbServer = NULL;
|
#endif
|
#endif
|
|
|
| Line 350... |
Line 334... |
#ifdef JTAG_DEBUG
|
#ifdef JTAG_DEBUG
|
jtag_tdi = 1; // Tie off the JTAG inputs
|
jtag_tdi = 1; // Tie off the JTAG inputs
|
jtag_tms = 1;
|
jtag_tms = 1;
|
#endif
|
#endif
|
|
|
if (VCD_enabled)
|
if (VCD_enabled) {
|
{
|
|
Verilated::traceEverOn (true);
|
Verilated::traceEverOn (true);
|
|
|
printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
|
printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
|
|
|
// Establish a new trace with its correct time resolution, and trace to
|
// Establish a new trace with its correct time resolution, and trace to
|
// great depth.
|
// great depth.
|
verilatorVCDFile = new VerilatedVcdC ();
|
verilatorVCDFile = new VerilatedVcdC ();
|
|
|
orpsoc->trace (verilatorVCDFile, dump_depth);
|
orpsoc->trace (verilatorVCDFile, dump_depth);
|
|
|
if (dumping_now)
|
if (dumping_now) {
|
{
|
|
verilatorVCDFile->open (vcdDumpFile.c_str());
|
verilatorVCDFile->open (vcdDumpFile.c_str());
|
}
|
}
|
}
|
}
|
|
|
//printf("* Beginning test\n");
|
//printf("* Beginning test\n");
|
|
|
#ifdef UART0
|
#ifdef UART0
|
// Init the UART function
|
// Init the UART function
|
uart->initUart(50000000, 115200);
|
uart->initUart(50000000, 115200);
|
#endif
|
#endif
|
|
|
if (do_program_file_load) // Did the user specify a file to load?
|
if (do_program_file_load) // Did the user specify a file to load?
|
{
|
{
|
cout << "* Loading program from " << program_file << endl;
|
if (!gQuiet)
|
if (memoryload->loadcode(program_file,0,0) < 0)
|
cout << "* Loading program from " << program_file <<
|
{
|
endl;
|
|
if (memoryload->loadcode(program_file, 0, 0) < 0) {
|
cout << "* Error: executable file " << program_file <<
|
cout << "* Error: executable file " << program_file <<
|
" not loaded" << endl;
|
" not loaded" << endl;
|
|
goto finish_up;
|
|
|
}
|
}
|
}
|
} else
|
else // No ELF file specified, default is to load SRAM from VMEM file
|
|
{
|
{
|
if (!quiet)
|
/* No ELF file specified, default is to load from VMEM file */
|
cout << "* Loading memory with image from default file, sram.vmem"
|
if (!gQuiet)
|
|
cout <<
|
|
"* Loading memory with image from default file, sram.vmem"
|
<< endl;
|
<< endl;
|
accessor->do_ram_readmemh();
|
accessor->do_ram_readmemh();
|
}
|
}
|
|
|
SIM_RUNNING = 1;
|
gSimRunning = 1;
|
|
|
// First check how we should run the sim.
|
// First check how we should run the sim.
|
if (VCD_enabled || finish_time_set)
|
if (VCD_enabled || finish_time_set) { // We'll run sim with step
|
{ // We'll run sim with step
|
|
|
|
if (!VCD_enabled && finish_time_set)
|
if (!VCD_enabled && finish_time_set) {
|
{
|
|
// We just run the sim until the set finish time
|
// We just run the sim until the set finish time
|
sc_start((double)(finish_time.to_double()), TIMESCALE_UNIT);
|
sc_start((double)(finish_time.to_double()),
|
SIM_RUNNING=0;
|
TIMESCALE_UNIT);
|
|
gSimRunning = 0;
|
sc_stop();
|
sc_stop();
|
// Print performance summary
|
// Print performance summary
|
monitor->perfSummary();
|
monitor->perfSummary();
|
// Do memdump if enabled
|
// Do memdump if enabled
|
monitor->memdump();
|
monitor->memdump();
|
}
|
} else {
|
else
|
if (dump_start_delay_set) {
|
{
|
|
if (dump_start_delay_set)
|
|
{
|
|
// Run the sim until we want to dump
|
// Run the sim until we want to dump
|
sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
|
sc_start((double)(dump_start.to_double()),
|
|
TIMESCALE_UNIT);
|
// Open the trace file
|
// Open the trace file
|
verilatorVCDFile->open (vcdDumpFile.c_str());
|
verilatorVCDFile->open (vcdDumpFile.c_str());
|
dumping_now = 1;
|
dumping_now = 1;
|
}
|
}
|
|
|
if (dumping_now)
|
if (dumping_now) {
|
{
|
|
// Step the sim and generate the trace
|
// Step the sim and generate the trace
|
// Execute until we stop
|
// Execute until we stop
|
while(!Verilated::gotFinish())
|
while (!Verilated::gotFinish()) {
|
{
|
// gSimRunning value changed by the
|
if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
|
// monitor when sim should finish.
|
sc_start (1,TIMESCALE_UNIT); // Step the sim
|
if (gSimRunning)
|
else
|
// Step the sim
|
{
|
sc_start(1, TIMESCALE_UNIT);
|
|
else {
|
verilatorVCDFile->close();
|
verilatorVCDFile->close();
|
break;
|
break;
|
}
|
}
|
|
|
verilatorVCDFile->dump (sc_time_stamp().to_double());
|
verilatorVCDFile->dump(sc_time_stamp().
|
|
to_double());
|
|
|
if (dump_stop_set)
|
if (dump_stop_set) {
|
{
|
if (sc_time_stamp() >=
|
if (sc_time_stamp() >= dump_stop)
|
dump_stop) {
|
{
|
|
// Close dump file
|
// Close dump file
|
verilatorVCDFile->close();
|
verilatorVCDFile->close
|
|
();
|
// Now continue on again until the end
|
// Now continue on again until the end
|
if (!finish_time_set)
|
if (!finish_time_set)
|
sc_start();
|
sc_start();
|
else
|
else {
|
{
|
|
// Determine how long we should run for
|
// Determine how long we should run for
|
sc_time sim_time_remaining =
|
sc_time
|
finish_time - sc_time_stamp();
|
sim_time_remaining
|
sc_start((double)(sim_time_remaining.to_double()),
|
=
|
TIMESCALE_UNIT);
|
finish_time
|
|
-
|
|
sc_time_stamp
|
|
();
|
|
sc_start((double)(sim_time_remaining.to_double()), TIMESCALE_UNIT);
|
// Officially stop the sim
|
// Officially stop the sim
|
sc_stop();
|
sc_stop();
|
// Print performance summary
|
// Print performance summary
|
monitor->perfSummary();
|
monitor->
|
|
perfSummary
|
|
();
|
// Do memdump if enabled
|
// Do memdump if enabled
|
monitor->memdump();
|
monitor->memdump
|
|
();
|
}
|
}
|
break;
|
break;
|
}
|
}
|
}
|
}
|
if (finish_time_set)
|
if (finish_time_set) {
|
{
|
if (sc_time_stamp() >=
|
if (sc_time_stamp() >= finish_time)
|
finish_time) {
|
{
|
|
// Officially stop the sim
|
// Officially stop the sim
|
sc_stop();
|
sc_stop();
|
// Close dump file
|
// Close dump file
|
verilatorVCDFile->close();
|
verilatorVCDFile->close
|
|
();
|
// Do memdump if enabled
|
// Do memdump if enabled
|
monitor->memdump();
|
monitor->memdump();
|
// Print performance summary
|
// Print performance summary
|
monitor->perfSummary();
|
monitor->perfSummary();
|
break;
|
break;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
} else {
|
else
|
|
{
|
|
// Simple run case
|
// Simple run case
|
// Ideally a "l.nop 1" will terminate the simulation gracefully.
|
// Ideally a "l.nop 1" will terminate the simulation gracefully.
|
// Need to step at clock period / 4, otherwise model appears to skip the
|
// Need to step at clock period / 4, otherwise model appears to skip the
|
// monitor and logging functions sometimes (?!?)
|
// monitor and logging functions sometimes (?!?)
|
while (SIM_RUNNING)
|
while (gSimRunning)
|
sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);
|
sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);
|
//sc_start();
|
//sc_start();
|
}
|
}
|
|
|
|
|
|
finish_up:
|
// Free memory
|
// Free memory
|
#ifdef JTAG_DEBUG
|
#ifdef JTAG_DEBUG
|
if (rsp_server_enabled)
|
if (rsp_server_enabled)
|
delete gdbServer;
|
delete gdbServer;
|
|
|
