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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Diff between revs 44 and 49

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Rev 44 Rev 49
Line 43... Line 43...
 
 
#include "OrpsocMain.h"
#include "OrpsocMain.h"
 
 
#include "Vorpsoc_top.h"
#include "Vorpsoc_top.h"
#include "OrpsocAccess.h"
#include "OrpsocAccess.h"
#include "TraceSC.h"
 
 
//#if VM_TRACE
 
//#include <systemc.h>
 
#include <SpTraceVcdC.h>
 
//#endif
 
 
 
//#include "TraceSC.h"
#include "ResetSC.h"
#include "ResetSC.h"
#include "Or1200MonitorSC.h"
#include "Or1200MonitorSC.h"
#include "UartSC.h"
#include "UartSC.h"
 
 
 
int SIM_RUNNING;
int sc_main (int   argc,
int sc_main (int   argc,
             char *argv[] )
             char *argv[] )
{
{
 
  sc_set_time_resolution( 1, TIMESCALE_UNIT);
  // CPU clock (also used as JTAG TCK) and reset (both active high and low)
  // CPU clock (also used as JTAG TCK) and reset (both active high and low)
  sc_time  clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
  sc_time  clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
 
 
  sc_clock             clk ("clk", clkPeriod);
  sc_clock             clk ("clk", clkPeriod);
  sc_signal<bool>      rst;
  sc_signal<bool>      rst;
Line 81... Line 87...
  sc_signal<bool> spi1_mosi;
  sc_signal<bool> spi1_mosi;
  sc_signal<bool> spi1_miso;
  sc_signal<bool> spi1_miso;
  sc_signal<bool> spi1_ss;
  sc_signal<bool> spi1_ss;
  sc_signal<bool> spi1_sclk;
  sc_signal<bool> spi1_sclk;
 
 
 
  SIM_RUNNING = 0;
 
 
 
  // Setup the name of the VCD dump file
 
  int VCD_enabled = 0;
 
  string dumpNameDefault("vlt-dump.vcd");
 
  string testNameString;
 
  string vcdDumpFile;
 
  // VCD dump controling vars
 
  int dump_start_delay, dump_stop_set;
 
  int dumping_now;
 
  int dump_depth = 99; // Default dump depth
 
  sc_time dump_start,dump_stop, finish_time;
 
  int finish_time_set = 0; // By default we will let the simulation finish naturally
 
  SpTraceVcdCFile *spTraceFile;
 
 
 
  int time_val;
 
  int cmdline_name_found=0;
 
 
  // Verilator accessor
  // Verilator accessor
  OrpsocAccess    *accessor;
  OrpsocAccess    *accessor;
 
 
  // Modules
  // Modules
  Vorpsoc_top *orpsoc;          // Verilated ORPSoC
  Vorpsoc_top *orpsoc;          // Verilated ORPSoC
  TraceSC          *trace;              // Drive VCD
  //TraceSC          *trace;            // Drive VCD
 
 
  ResetSC          *reset;              // Generate a RESET signal
  ResetSC          *reset;              // Generate a RESET signal
  Or1200MonitorSC  *monitor;            // Handle l.nop x instructions
  Or1200MonitorSC  *monitor;            // Handle l.nop x instructions
  UartSC          *uart;                // Handle UART signals
  UartSC          *uart;                // Handle UART signals
 
 
  // Instantiate the Verilator model, VCD trace handler and accessor
  // Instantiate the Verilator model, VCD trace handler and accessor
  orpsoc     = new Vorpsoc_top ("orpsoc");
  orpsoc     = new Vorpsoc_top ("orpsoc");
  trace      = new TraceSC ("trace", orpsoc, argc, argv);
  //trace      = new TraceSC ("trace", orpsoc, argc, argv);
  accessor   = new OrpsocAccess (orpsoc);
  accessor   = new OrpsocAccess (orpsoc);
 
 
  // Instantiate the SystemC modules
  // Instantiate the SystemC modules
  reset         = new ResetSC ("reset", BENCH_RESET_TIME);
  reset         = new ResetSC ("reset", BENCH_RESET_TIME);
  monitor       = new Or1200MonitorSC ("monitor", accessor);
  monitor       = new Or1200MonitorSC ("monitor", accessor, argc, argv);
  uart          = new UartSC("uart"); // TODO: Probalby some sort of param
  uart          = new UartSC("uart"); // TODO: Probalby some sort of param
 
 
 
 
 
  // Parse command line options
 
  // Default is for VCD generation OFF, only turned on if specified on command line
 
  dump_start_delay = 0;
 
  dump_stop_set = 0;
 
  dumping_now = 0;
 
 
 
 
 
  // Search through the command line parameters for  options
 
 
 
  if (argc > 1)
 
    {
 
      for(int i=1; i<argc; i++)
 
        {
 
          if ((strcmp(argv[i], "-d")==0) ||
 
              (strcmp(argv[i], "--vcdfile")==0))
 
            {
 
              testNameString = (argv[i+1]);
 
              vcdDumpFile = testNameString;
 
              cmdline_name_found=1;
 
            }
 
          else if ((strcmp(argv[i], "-v")==0) ||
 
                   (strcmp(argv[i], "--vcdon")==0))
 
            {
 
              dumping_now = 1;
 
            }
 
          else if ( (strcmp(argv[i], "-e")==0) ||
 
                    (strcmp(argv[i], "--endtime")==0) )
 
            {
 
              time_val = atoi(argv[i+1]);
 
              sc_time opt_end_time(time_val,TIMESCALE_UNIT);
 
              finish_time = opt_end_time;
 
              //if (DEBUG_TRACESC) cout << "* Commmand line opt: Sim. will end at " << finish_time.to_string() << endl;
 
              finish_time_set = 1;
 
            }
 
          //#if VM_TRACE  
 
          else if ( (strcmp(argv[i], "-s")==0) ||
 
                    (strcmp(argv[i], "--vcdstart")==0) )
 
            {
 
              time_val = atoi(argv[i+1]);
 
              sc_time dump_start_time(time_val,TIMESCALE_UNIT);
 
              dump_start = dump_start_time;
 
              //if (DEBUG_TRACESC) cout << "* Commmand line opt: Dump start time set at " << dump_start.to_string() << endl;
 
              dump_start_delay = 1;
 
              dumping_now = 0;
 
            }
 
          else if ( (strcmp(argv[i], "-t")==0) ||
 
                    (strcmp(argv[i], "--vcdstop")==0) )
 
            {
 
              time_val = atoi(argv[i+1]);
 
              sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
 
              dump_stop = dump_stop_time;
 
              //if (DEBUG_TRACESC) cout << "* Commmand line opt: Dump stop time set at " << dump_stop.to_string() << endl;
 
              dump_stop_set = 1;
 
            }
 
          /* Depth setting of VCD doesn't appear to work, I think it's set during verilator script compile time */
 
          /*      else if ( (strcmp(argv[i], "-p")==0) ||
 
                    (strcmp(argv[i], "--vcddepth")==0) )
 
            {
 
              dump_depth = atoi(argv[i+1]);
 
              //if (DEBUG_TRACESC) cout << "* Commmand line opt: Dump depth set to " << dump_depth << endl;
 
              }*/
 
          else if ( (strcmp(argv[i], "-h")==0) ||
 
                    (strcmp(argv[i], "--help")==0) )
 
            {
 
              printf("\n  ORPSoC Cycle Accurate model usage:\n");
 
              printf("  %s [-vh] [-d <file>] [-e <time>] [-s <time>] [-t <time>]",argv[0]);
 
              monitor->printSwitches();
 
              printf("\n\n");
 
              printf("  -h, --help\t\tPrint this help message\n");
 
              printf("  -e, --endtime\t\tStop the sim at this time (ns)\n");
 
              printf("  -v, --vcdon\t\tEnable VCD generation\n");
 
              printf("  -d, --vcdfile\t\tEnable and specify target VCD file name\n");
 
 
 
              printf("  -s, --vcdstart\tEnable and delay VCD generation until this time (ns)\n");
 
              printf("  -t, --vcdstop\t\tEnable and terminate VCD generation at this time (ns)\n");
 
              monitor->printUsage();
 
              printf("\n");
 
              return 0;
 
            }
 
 
 
        }
 
    }
 
 
 
  if(cmdline_name_found==0) // otherwise use our default VCD dump file name
 
    vcdDumpFile = dumpNameDefault;
 
 
 
  // Determine if we're going to setup a VCD dump:
 
  // Pretty much setting any option will enable VCD dumping.
 
  if ((cmdline_name_found) || (dumping_now) || (dump_start_delay) || (dump_stop_set))
 
    {
 
      VCD_enabled = 1;
 
 
 
      cout << "* Enabling VCD trace";
 
 
 
      if (dump_start_delay)
 
        cout << ", on at time " << dump_start.to_string();
 
      if (dump_stop_set)
 
    cout << ", off at time " << dump_stop.to_string();
 
      cout << endl;
 
    }
 
 
 
 
  // Connect up ORPSoC
  // Connect up ORPSoC
  orpsoc->clk_pad_i (clk);
  orpsoc->clk_pad_i (clk);
  orpsoc->rst_pad_i (rstn);
  orpsoc->rst_pad_i (rstn);
  orpsoc->rst_pad_o (rst_o);
  orpsoc->rst_pad_o (rst_o);
 
 
Line 130... Line 256...
 
 
 
 
  orpsoc->gpio_a_pad_io (gpio_a); // GPIO bus - output only in 
  orpsoc->gpio_a_pad_io (gpio_a); // GPIO bus - output only in 
                                  // verilator sims
                                  // verilator sims
 
 
 
 
  // Connect up the VCD trace handler
  // Connect up the VCD trace handler
  trace->clk (clk);                     // Trace
  //trace->clk (clk);                   // Trace
 
 
  // Connect up the SystemC  modules
  // Connect up the SystemC  modules
  reset->clk (clk);                     // Reset
  reset->clk (clk);                     // Reset
  reset->rst (rst);
  reset->rst (rst);
  reset->rstn (rstn);
  reset->rstn (rstn);
Line 153... Line 278...
 
 
   spi_sd_miso = 0; // Tie off master-in/slave-out of SD SPI bus
   spi_sd_miso = 0; // Tie off master-in/slave-out of SD SPI bus
 
 
  spi1_miso = 0;
  spi1_miso = 0;
 
 
  printf("Beginning test\n");
  //#if VM_TRACE  
 
  if (VCD_enabled)
 
    {
 
      Verilated::traceEverOn (true);
 
 
 
      printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
 
 
 
      // Establish a new trace with its correct time resolution, and trace to
 
      // great depth.
 
      spTraceFile = new SpTraceVcdCFile ();
 
      //spTraceFile->spTrace()->set_time_resolution (sc_get_time_resolution());
 
      //setSpTimeResolution (sc_get_time_resolution ());
 
      //traceTarget->trace (spTraceFile, 99);
 
      orpsoc->trace (spTraceFile, dump_depth);
 
 
 
      if (dumping_now)
 
        {
 
          spTraceFile->open (vcdDumpFile.c_str());
 
        }
 
      //#endif
 
    }
 
 
 
  printf("* Beginning test\n");
 
 
  // Init the UART function
  // Init the UART function
  uart->initUart(25000000, 115200);
  uart->initUart(25000000, 115200);
 
 
  // Turn on logging by setting the "-log logfilename" option on the command line
  SIM_RUNNING = 1;
  monitor->init_displayState(argc, argv);
 
 
  // First check how we should run the sim.
 
  if (VCD_enabled || finish_time_set)
 
    { // We'll run sim with step
 
 
 
      if (!VCD_enabled && finish_time_set)
 
        {
 
          // We just run the sim until the set finish time
 
          sc_start((double)(finish_time.to_double()), TIMESCALE_UNIT);
 
          SIM_RUNNING=0;
 
          sc_stop();
 
          // Print performance summary
 
          monitor->perfSummary();
 
        }
 
      else
 
        {
 
          if (dump_start_delay)
 
            {
 
              // Run the sim until we want to dump
 
              sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
 
              // Open the trace file
 
              spTraceFile->open (vcdDumpFile.c_str());
 
              dumping_now = 1;
 
            }
 
 
 
          if (dumping_now)
 
            {
 
              // Step the sim and generate the trace
  // Execute until we stop
  // Execute until we stop
 
              while(!Verilated::gotFinish())
 
                {
 
                  if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
 
                    sc_start (1,TIMESCALE_UNIT); // Step the sim
 
                  else
 
                    {
 
                      spTraceFile->close();
 
                      break;
 
                    }
 
 
 
                  spTraceFile->dump (sc_time_stamp().to_double());
 
 
 
                  if (dump_stop_set)
 
                    {
 
                      if (sc_time_stamp() >=  dump_stop)
 
                        {
 
                          // Close dump file
 
                          spTraceFile->close();
 
                          // Now continue on again until the end
 
                          if (!finish_time_set)
  sc_start ();
  sc_start ();
 
                          else
 
                            {
 
                              // Determine how long we should run for
 
                              sc_time sim_time_remaining =
 
                                finish_time - sc_time_stamp();
 
                              sc_start((double)(sim_time_remaining.to_double()),
 
                                       TIMESCALE_UNIT);
 
                              // Officially stop the sim
 
                              sc_stop();
 
                              // Print performance summary
 
                              monitor->perfSummary();
 
                            }
 
                          break;
 
                        }
 
                    }
 
                  if (finish_time_set)
 
                    {
 
                      if (sc_time_stamp() >=  finish_time)
 
                        {
 
                          // Officially stop the sim
 
                          sc_stop();
 
                          // Close dump file
 
                          spTraceFile->close();
 
                          // Print performance summary
 
                          monitor->perfSummary();
 
                          break;
 
                        }
 
                    }
 
                }
 
            }
 
        }
 
    }
 
  else
 
    {
 
      // Simple run case
 
      sc_start();
 
    }
 
 
 
 
  // Free memory
  // Free memory
  delete monitor;
  delete monitor;
  delete reset;
  delete reset;
 
 
  delete accessor;
  delete accessor;
 
 
  delete trace;
  //delete trace;
  delete orpsoc;
  delete orpsoc;
 
 
  return 0;
  return 0;
 
 
}       /* sc_main() */
}       /* sc_main() */

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