URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Diff between revs 51 and 52

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Rev 51	Rev 52
Line 306...	Line 306...
`spTraceFile->open (vcdDumpFile.c_str());`	`spTraceFile->open (vcdDumpFile.c_str());`
`}`	`}`
`//#endif`	`//#endif`
`}`	`}`

`printf("* Beginning test\n");`	`//printf("* Beginning test\n");`

`// Init the UART function`	`// Init the UART function`
`uart->initUart(25000000, 115200);`	`uart->initUart(25000000, 115200);`

`if (do_program_file_load) // Did the user specify a file to load?`	`if (do_program_file_load) // Did the user specify a file to load?`
Line 338...	Line 338...
`sc_start((double)(finish_time.to_double()), TIMESCALE_UNIT);`	`sc_start((double)(finish_time.to_double()), TIMESCALE_UNIT);`
`SIM_RUNNING=0;`	`SIM_RUNNING=0;`
`sc_stop();`	`sc_stop();`
`// Print performance summary`	`// Print performance summary`
`monitor->perfSummary();`	`monitor->perfSummary();`
	`// Do memdump if enabled`
	`monitor->memdump();`
`}`	`}`
`else`	`else`
`{`	`{`
`if (dump_start_delay)`	`if (dump_start_delay)`
`{`	`{`
Line 386...	Line 388...
`TIMESCALE_UNIT);`	`TIMESCALE_UNIT);`
`// Officially stop the sim`	`// Officially stop the sim`
`sc_stop();`	`sc_stop();`
`// Print performance summary`	`// Print performance summary`
`monitor->perfSummary();`	`monitor->perfSummary();`
	`// Do memdump if enabled`
	`monitor->memdump();`
`}`	`}`
`break;`	`break;`
`}`	`}`
`}`	`}`
`if (finish_time_set)`	`if (finish_time_set)`
Line 398...	Line 402...
`{`	`{`
`// Officially stop the sim`	`// Officially stop the sim`
`sc_stop();`	`sc_stop();`
`// Close dump file`	`// Close dump file`
`spTraceFile->close();`	`spTraceFile->close();`
	`// Do memdump if enabled`
	`monitor->memdump();`
`// Print performance summary`	`// Print performance summary`
`monitor->perfSummary();`	`monitor->perfSummary();`
`break;`	`break;`
`}`	`}`
`}`	`}`
Line 410...	Line 416...
`}`	`}`
`}`	`}`
`else`	`else`
`{`	`{`
`// Simple run case`	`// Simple run case`
	`// Ideally a "l.nop 1" will terminate the simulation gracefully`
`sc_start();`	`sc_start();`
`}`	`}`


`// Free memory`	`// Free memory`

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Diff between revs 51 and 52