| Line 40... |
Line 40... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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#include "OrpsocMain.h"
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#include "OrpsocMain.h"
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#include "JtagSC_includes.h"
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// TODO - copy orpsoc-defines.h and or1200-defines.h somewhere this can see
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// them and include/exclude RSP stuff. For now is defined
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//#define JTAG_DEBUG
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#include "Vorpsoc_top.h"
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#include "Vorpsoc_top.h"
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#include "OrpsocAccess.h"
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#include "OrpsocAccess.h"
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#include "MemoryLoad.h"
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#include "MemoryLoad.h"
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#include <verilated_vcd_c.h>
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#include <verilated_vcd_c.h>
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#include "ResetSC.h"
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#include "ResetSC.h"
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#include "Or1200MonitorSC.h"
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#include "Or1200MonitorSC.h"
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#ifdef JTAG_DEBUG
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#include "GdbServerSC.h"
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#include "GdbServerSC.h"
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# include "JtagSC_includes.h"
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#endif
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#include "UartSC.h"
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#include "UartSC.h"
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int SIM_RUNNING;
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int SIM_RUNNING;
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int sc_main (int argc,
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int sc_main (int argc,
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char *argv[] )
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char *argv[] )
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{
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{
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sc_set_time_resolution( 1, TIMESCALE_UNIT);
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sc_set_time_resolution( 1, TIMESCALE_UNIT);
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// CPU clock (also used as JTAG TCK) and reset (both active high and low)
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// CPU clock (also used as JTAG TCK) and reset (both active high and low)
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sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
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sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
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sc_time jtagPeriod (JTAG_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
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sc_clock clk ("clk", clkPeriod);
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sc_clock clk ("clk", clkPeriod);
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sc_clock jtag_tck ("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
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sc_signal<bool> rst;
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sc_signal<bool> rst;
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sc_signal<bool> rstn;
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sc_signal<bool> rstn;
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#ifdef JTAG_DEBUG
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sc_time jtagPeriod (JTAG_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
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sc_clock jtag_tck ("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
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sc_signal<bool> jtag_tdi; // JTAG interface
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sc_signal<bool> jtag_tdi; // JTAG interface
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sc_signal<bool> jtag_tdo;
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sc_signal<bool> jtag_tdo;
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sc_signal<bool> jtag_tms;
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sc_signal<bool> jtag_tms;
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sc_signal<bool> jtag_trst;
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sc_signal<bool> jtag_trst;
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#endif
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sc_signal<bool> uart_rx; // External UART
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sc_signal<bool> uart_rx; // External UART
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sc_signal<bool> uart_tx;
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sc_signal<bool> uart_tx;
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SIM_RUNNING = 0;
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SIM_RUNNING = 0;
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| Line 88... |
Line 97... |
// VCD dump controling vars
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// VCD dump controling vars
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bool dump_start_delay_set = false, dump_stop_set = false;
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bool dump_start_delay_set = false, dump_stop_set = false;
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bool dumping_now = false;
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bool dumping_now = false;
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int dump_depth = 99; // Default dump depth
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int dump_depth = 99; // Default dump depth
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sc_time dump_start,dump_stop, finish_time;
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sc_time dump_start,dump_stop, finish_time;
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bool finish_time_set = false; // By default we will let the simulation finish naturally
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bool finish_time_set = false; // By default we will let the simulation
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// finish naturally
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VerilatedVcdC *verilatorVCDFile;
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VerilatedVcdC *verilatorVCDFile;
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/*int*/double time_val;
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/*int*/double time_val;
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bool vcd_file_name_given = false;
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bool vcd_file_name_given = false;
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#ifdef JTAG_DEBUG
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bool rsp_server_enabled = false;
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bool rsp_server_enabled = false;
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int rsp_server_port = DEFAULT_RSP_PORT;
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int rsp_server_port = DEFAULT_RSP_PORT;
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#endif
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// Executable app load variables
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// Executable app load variables
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int do_program_file_load = 0; // Default: we don't require a file, we use the VMEM
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int do_program_file_load = 0; // Default: we don't require a file, we use the
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// VMEM
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char* program_file; // Old char* style for program name
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char* program_file; // Old char* style for program name
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// Verilator accessor
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// Verilator accessor
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OrpsocAccess *accessor;
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OrpsocAccess *accessor;
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| Line 110... |
Line 123... |
Vorpsoc_top *orpsoc; // Verilated ORPSoC
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Vorpsoc_top *orpsoc; // Verilated ORPSoC
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MemoryLoad *memoryload; // Memory loader
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MemoryLoad *memoryload; // Memory loader
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ResetSC *reset; // Generate a RESET signal
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ResetSC *reset; // Generate a RESET signal
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Or1200MonitorSC *monitor; // Handle l.nop x instructions
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Or1200MonitorSC *monitor; // Handle l.nop x instructions
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#ifdef JTAG_DEBUG
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JtagSC *jtag; // Generate JTAG signals
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JtagSC *jtag; // Generate JTAG signals
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GdbServerSC *gdbServer; // Map RSP requests to debug unit
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GdbServerSC *gdbServer; // Map RSP requests to debug unit
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#endif
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UartSC *uart; // Handle UART signals
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UartSC *uart; // Handle UART signals
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// Instantiate the Verilator model, VCD trace handler and accessor
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// Instantiate the Verilator model, VCD trace handler and accessor
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orpsoc = new Vorpsoc_top ("orpsoc");
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orpsoc = new Vorpsoc_top ("orpsoc");
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| Line 128... |
Line 146... |
argc, argv);
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argc, argv);
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// Instantiate the SystemC modules
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// Instantiate the SystemC modules
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reset = new ResetSC ("reset", BENCH_RESET_TIME);
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reset = new ResetSC ("reset", BENCH_RESET_TIME);
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#ifdef JTAG_DEBUG
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jtag = new JtagSC ("jtag");
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jtag = new JtagSC ("jtag");
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#endif
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uart = new UartSC("uart"); // TODO: Probalby some sort of param
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uart = new UartSC("uart"); // TODO: Probalby some sort of param
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// Parse command line options
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// Parse command line options
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// Default is for VCD generation OFF, only turned on if specified on command line
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// Default is for VCD generation OFF, only turned on if specified on command
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// line
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// Search through the command line parameters for options
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// Search through the command line parameters for options
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if (argc > 1)
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if (argc > 1)
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{
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{
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for(int i=1; i<argc; i++)
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for(int i=1; i<argc; i++)
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| Line 151... |
Line 172... |
finish_time_set = true;
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finish_time_set = true;
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}
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}
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else if ( (strcmp(argv[i], "-f")==0) ||
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else if ( (strcmp(argv[i], "-f")==0) ||
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(strcmp(argv[i], "--program")==0) )
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(strcmp(argv[i], "--program")==0) )
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{
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{
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do_program_file_load = 1; // Enable program loading - will be done after sim init
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do_program_file_load = 1; // Enable program loading - will be
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// done after sim init.
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program_file = argv[i+1]; // Old char* style for program name
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program_file = argv[i+1]; // Old char* style for program name
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}
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}
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else if ((strcmp(argv[i], "-d")==0) ||
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else if ((strcmp(argv[i], "-d")==0) ||
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(strcmp(argv[i], "--vcdfile")==0) ||
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(strcmp(argv[i], "--vcdfile")==0) ||
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(strcmp(argv[i], "-v")==0) ||
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(strcmp(argv[i], "-v")==0) ||
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Line 212... |
time_val = strtod(argv[i+1],NULL);
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time_val = strtod(argv[i+1],NULL);
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sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
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sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
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dump_stop = dump_stop_time;
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dump_stop = dump_stop_time;
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dump_stop_set = true;
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dump_stop_set = true;
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}
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}
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#ifdef JTAG_DEBUG
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else if ( (strcmp(argv[i], "-r")==0) ||
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else if ( (strcmp(argv[i], "-r")==0) ||
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(strcmp(argv[i], "--rsp")==0) )
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(strcmp(argv[i], "--rsp")==0) )
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{
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{
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rsp_server_enabled = true;
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rsp_server_enabled = true;
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if (i+1 < argc) if(argv[i+1][0] != '-')
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if (i+1 < argc) if(argv[i+1][0] != '-')
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{
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{
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rsp_server_port = atoi(argv[i+1]);
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rsp_server_port = atoi(argv[i+1]);
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i++;
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i++;
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}
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}
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}
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}
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#endif
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/*
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/*
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Depth setting of VCD doesn't appear to work, I think it's only
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Depth setting of VCD doesn't appear to work, I think it's only
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configurable during at compile time .
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configurable during at compile time .
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*/
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*/
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/* else if ( (strcmp(argv[i], "-p")==0) ||
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/* else if ( (strcmp(argv[i], "-p")==0) ||
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| Line 227... |
Line 251... |
printf(" -v, --vcdon\t\tEnable VCD generation\n");
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printf(" -v, --vcdon\t\tEnable VCD generation\n");
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printf(" -d, --vcdfile <file>\tEnable and save VCD to <file>\n");
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printf(" -d, --vcdfile <file>\tEnable and save VCD to <file>\n");
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printf(" -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");
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printf(" -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");
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printf(" -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");
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printf(" -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");
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#ifdef JTAG_DEBUG
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printf("\nRemote debugging:\n");
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printf("\nRemote debugging:\n");
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printf(" -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");
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printf(" -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");
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#endif
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monitor->printUsage();
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monitor->printUsage();
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printf("\n");
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printf("\n");
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return 0;
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return 0;
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}
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}
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| Line 250... |
Line 276... |
cout << ", on at time " << dump_start.to_string();
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cout << ", on at time " << dump_start.to_string();
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if (dump_stop_set)
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if (dump_stop_set)
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cout << ", off at time " << dump_stop.to_string();
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cout << ", off at time " << dump_stop.to_string();
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cout << endl;
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cout << endl;
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}
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}
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#ifdef JTAG_DEBUG
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if (rsp_server_enabled)
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if (rsp_server_enabled)
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gdbServer = new GdbServerSC ("gdb-server", FLASH_START, FLASH_END,
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gdbServer = new GdbServerSC ("gdb-server", FLASH_START, FLASH_END,
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rsp_server_port, jtag->tapActionQueue);
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rsp_server_port, jtag->tapActionQueue);
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else
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else
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gdbServer = NULL;
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gdbServer = NULL;
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#endif
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// Connect up ORPSoC
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// Connect up ORPSoC
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orpsoc->clk_pad_i (clk);
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orpsoc->clk_pad_i (clk);
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orpsoc->rst_n_pad_i (rstn);
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orpsoc->rst_n_pad_i (rstn);
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#ifdef JTAG_DEBUG
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orpsoc->tck_pad_i (jtag_tck); // JTAG interface
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orpsoc->tck_pad_i (jtag_tck); // JTAG interface
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orpsoc->tdi_pad_i (jtag_tdi);
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orpsoc->tdi_pad_i (jtag_tdi);
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orpsoc->tms_pad_i (jtag_tms);
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orpsoc->tms_pad_i (jtag_tms);
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orpsoc->tdo_pad_o (jtag_tdo);
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orpsoc->tdo_pad_o (jtag_tdo);
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#endif
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orpsoc->uart0_srx_pad_i (uart_rx); // External UART
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orpsoc->uart0_srx_pad_i (uart_rx); // External UART
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orpsoc->uart0_stx_pad_o (uart_tx);
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orpsoc->uart0_stx_pad_o (uart_tx);
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// Connect up the SystemC modules
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// Connect up the SystemC modules
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| Line 276... |
Line 305... |
reset->rst (rst);
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reset->rst (rst);
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reset->rstn (rstn);
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reset->rstn (rstn);
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monitor->clk (clk); // Monitor
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monitor->clk (clk); // Monitor
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#ifdef JTAG_DEBUG
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jtag->sysReset (rst); // JTAG
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jtag->sysReset (rst); // JTAG
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jtag->tck (jtag_tck);
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jtag->tck (jtag_tck);
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jtag->tdi (jtag_tdi);
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jtag->tdi (jtag_tdi);
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jtag->tdo (jtag_tdo);
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jtag->tdo (jtag_tdo);
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jtag->tms (jtag_tms);
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jtag->tms (jtag_tms);
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jtag->trst (jtag_trst);
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jtag->trst (jtag_trst);
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#endif
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uart->clk (clk); // Uart
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uart->clk (clk); // Uart
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uart->uartrx (uart_rx); // orpsoc's receive line
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uart->uartrx (uart_rx); // orpsoc's receive line
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uart->uarttx (uart_tx); // orpsoc's transmit line
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uart->uarttx (uart_tx); // orpsoc's transmit line
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// Tie off signals
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// Tie off signals
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#ifdef JTAG_DEBUG
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jtag_tdi = 1; // Tie off the JTAG inputs
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jtag_tdi = 1; // Tie off the JTAG inputs
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jtag_tms = 1;
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jtag_tms = 1;
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#endif
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if (VCD_enabled)
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if (VCD_enabled)
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{
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{
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Verilated::traceEverOn (true);
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Verilated::traceEverOn (true);
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printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
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printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
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// Establish a new trace with its correct time resolution, and trace to
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// Establish a new trace with its correct time resolution, and trace to
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// great depth.
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// great depth.
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verilatorVCDFile = new VerilatedVcdC ();
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verilatorVCDFile = new VerilatedVcdC ();
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//verilatorVCDFile->verilated()->set_time_resolution (sc_get_time_resolution());
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//setSpTimeResolution (sc_get_time_resolution ());
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//traceTarget->trace (verilatorVCDFile, 99);
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orpsoc->trace (verilatorVCDFile, dump_depth);
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orpsoc->trace (verilatorVCDFile, dump_depth);
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if (dumping_now)
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if (dumping_now)
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{
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{
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verilatorVCDFile->open (vcdDumpFile.c_str());
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verilatorVCDFile->open (vcdDumpFile.c_str());
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| Line 321... |
Line 352... |
if (do_program_file_load) // Did the user specify a file to load?
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if (do_program_file_load) // Did the user specify a file to load?
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{
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{
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cout << "* Loading program from " << program_file << endl;
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cout << "* Loading program from " << program_file << endl;
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if (memoryload->loadcode(program_file,0,0) < 0)
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if (memoryload->loadcode(program_file,0,0) < 0)
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{
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{
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cout << "* Error: executable file " << program_file << " not loaded" << endl;
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cout << "* Error: executable file " << program_file <<
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" not loaded" << endl;
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}
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}
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}
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}
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else // Load SRAM from VMEM file
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else // Load SRAM from VMEM file
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{
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{
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accessor->do_ram_readmemh();
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accessor->do_ram_readmemh();
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| Line 421... |
Line 453... |
}
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}
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}
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}
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else
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else
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{
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{
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// Simple run case
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// Simple run case
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// Ideally a "l.nop 1" will terminate the simulation gracefully
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// Ideally a "l.nop 1" will terminate the simulation gracefully.
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// Need to step at clock period / 4, otherwise model appears to skip the monitor and logging functions sometimes (?!?)
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// Need to step at clock period / 4, otherwise model appears to skip the
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// monitor and logging functions sometimes (?!?)
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while (SIM_RUNNING)
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while (SIM_RUNNING)
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sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);
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sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);
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//sc_start();
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//sc_start();
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}
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}
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// Free memory
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// Free memory
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#ifdef JTAG_DEBUG
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if (rsp_server_enabled)
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if (rsp_server_enabled)
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delete gdbServer;
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delete gdbServer;
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delete jtag;
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delete jtag;
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#endif
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delete monitor;
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delete monitor;
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delete reset;
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delete reset;
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delete accessor;
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delete accessor;
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//delete trace;
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//delete trace;
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delete orpsoc;
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delete orpsoc;
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return 0;
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return 0;
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} /* sc_main() */
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} /* sc_main() */
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