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Line 43... |
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#include "OrpsocMain.h"
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#include "OrpsocMain.h"
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#include "Vorpsoc_top.h"
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#include "Vorpsoc_top.h"
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#include "OrpsocAccess.h"
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#include "OrpsocAccess.h"
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#include "TraceSC.h"
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//#if VM_TRACE
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//#include <systemc.h>
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#include <SpTraceVcdC.h>
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//#endif
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//#include "TraceSC.h"
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#include "ResetSC.h"
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#include "ResetSC.h"
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#include "Or1200MonitorSC.h"
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#include "Or1200MonitorSC.h"
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#include "UartSC.h"
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#include "UartSC.h"
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int SIM_RUNNING;
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int sc_main (int argc,
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int sc_main (int argc,
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char *argv[] )
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char *argv[] )
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{
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{
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sc_set_time_resolution( 1, TIMESCALE_UNIT);
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// CPU clock (also used as JTAG TCK) and reset (both active high and low)
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// CPU clock (also used as JTAG TCK) and reset (both active high and low)
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sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
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sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
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sc_clock clk ("clk", clkPeriod);
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sc_clock clk ("clk", clkPeriod);
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sc_signal<bool> rst;
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sc_signal<bool> rst;
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Line 87... |
sc_signal<bool> spi1_mosi;
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sc_signal<bool> spi1_mosi;
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sc_signal<bool> spi1_miso;
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sc_signal<bool> spi1_miso;
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sc_signal<bool> spi1_ss;
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sc_signal<bool> spi1_ss;
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sc_signal<bool> spi1_sclk;
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sc_signal<bool> spi1_sclk;
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SIM_RUNNING = 0;
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// Setup the name of the VCD dump file
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int VCD_enabled = 0;
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string dumpNameDefault("vlt-dump.vcd");
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string testNameString;
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string vcdDumpFile;
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// VCD dump controling vars
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int dump_start_delay, dump_stop_set;
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int dumping_now;
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int dump_depth = 99; // Default dump depth
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sc_time dump_start,dump_stop, finish_time;
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int finish_time_set = 0; // By default we will let the simulation finish naturally
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SpTraceVcdCFile *spTraceFile;
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int time_val;
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int cmdline_name_found=0;
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// Verilator accessor
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// Verilator accessor
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OrpsocAccess *accessor;
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OrpsocAccess *accessor;
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// Modules
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// Modules
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Vorpsoc_top *orpsoc; // Verilated ORPSoC
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Vorpsoc_top *orpsoc; // Verilated ORPSoC
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TraceSC *trace; // Drive VCD
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//TraceSC *trace; // Drive VCD
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ResetSC *reset; // Generate a RESET signal
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ResetSC *reset; // Generate a RESET signal
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Or1200MonitorSC *monitor; // Handle l.nop x instructions
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Or1200MonitorSC *monitor; // Handle l.nop x instructions
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UartSC *uart; // Handle UART signals
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UartSC *uart; // Handle UART signals
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// Instantiate the Verilator model, VCD trace handler and accessor
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// Instantiate the Verilator model, VCD trace handler and accessor
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orpsoc = new Vorpsoc_top ("orpsoc");
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orpsoc = new Vorpsoc_top ("orpsoc");
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trace = new TraceSC ("trace", orpsoc, argc, argv);
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//trace = new TraceSC ("trace", orpsoc, argc, argv);
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accessor = new OrpsocAccess (orpsoc);
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accessor = new OrpsocAccess (orpsoc);
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// Instantiate the SystemC modules
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// Instantiate the SystemC modules
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reset = new ResetSC ("reset", BENCH_RESET_TIME);
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reset = new ResetSC ("reset", BENCH_RESET_TIME);
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monitor = new Or1200MonitorSC ("monitor", accessor);
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monitor = new Or1200MonitorSC ("monitor", accessor, argc, argv);
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uart = new UartSC("uart"); // TODO: Probalby some sort of param
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uart = new UartSC("uart"); // TODO: Probalby some sort of param
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// Parse command line options
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// Default is for VCD generation OFF, only turned on if specified on command line
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dump_start_delay = 0;
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dump_stop_set = 0;
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dumping_now = 0;
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// Search through the command line parameters for options
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if (argc > 1)
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{
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for(int i=1; i<argc; i++)
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{
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if ((strcmp(argv[i], "-d")==0) ||
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(strcmp(argv[i], "--vcdfile")==0))
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{
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testNameString = (argv[i+1]);
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vcdDumpFile = testNameString;
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cmdline_name_found=1;
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}
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else if ((strcmp(argv[i], "-v")==0) ||
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(strcmp(argv[i], "--vcdon")==0))
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{
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dumping_now = 1;
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}
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else if ( (strcmp(argv[i], "-e")==0) ||
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(strcmp(argv[i], "--endtime")==0) )
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{
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time_val = atoi(argv[i+1]);
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sc_time opt_end_time(time_val,TIMESCALE_UNIT);
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finish_time = opt_end_time;
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//if (DEBUG_TRACESC) cout << "* Commmand line opt: Sim. will end at " << finish_time.to_string() << endl;
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finish_time_set = 1;
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}
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//#if VM_TRACE
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else if ( (strcmp(argv[i], "-s")==0) ||
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(strcmp(argv[i], "--vcdstart")==0) )
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{
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time_val = atoi(argv[i+1]);
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sc_time dump_start_time(time_val,TIMESCALE_UNIT);
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dump_start = dump_start_time;
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//if (DEBUG_TRACESC) cout << "* Commmand line opt: Dump start time set at " << dump_start.to_string() << endl;
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dump_start_delay = 1;
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dumping_now = 0;
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}
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else if ( (strcmp(argv[i], "-t")==0) ||
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(strcmp(argv[i], "--vcdstop")==0) )
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{
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time_val = atoi(argv[i+1]);
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sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
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dump_stop = dump_stop_time;
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//if (DEBUG_TRACESC) cout << "* Commmand line opt: Dump stop time set at " << dump_stop.to_string() << endl;
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dump_stop_set = 1;
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}
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/* Depth setting of VCD doesn't appear to work, I think it's set during verilator script compile time */
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/* else if ( (strcmp(argv[i], "-p")==0) ||
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(strcmp(argv[i], "--vcddepth")==0) )
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{
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dump_depth = atoi(argv[i+1]);
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//if (DEBUG_TRACESC) cout << "* Commmand line opt: Dump depth set to " << dump_depth << endl;
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}*/
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else if ( (strcmp(argv[i], "-h")==0) ||
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(strcmp(argv[i], "--help")==0) )
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{
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printf("\n ORPSoC Cycle Accurate model usage:\n");
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printf(" %s [-vh] [-d <file>] [-e <time>] [-s <time>] [-t <time>]",argv[0]);
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monitor->printSwitches();
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printf("\n\n");
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printf(" -h, --help\t\tPrint this help message\n");
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printf(" -e, --endtime\t\tStop the sim at this time (ns)\n");
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printf(" -v, --vcdon\t\tEnable VCD generation\n");
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printf(" -d, --vcdfile\t\tEnable and specify target VCD file name\n");
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printf(" -s, --vcdstart\tEnable and delay VCD generation until this time (ns)\n");
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printf(" -t, --vcdstop\t\tEnable and terminate VCD generation at this time (ns)\n");
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monitor->printUsage();
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printf("\n");
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return 0;
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}
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}
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}
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if(cmdline_name_found==0) // otherwise use our default VCD dump file name
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vcdDumpFile = dumpNameDefault;
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// Determine if we're going to setup a VCD dump:
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// Pretty much setting any option will enable VCD dumping.
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if ((cmdline_name_found) || (dumping_now) || (dump_start_delay) || (dump_stop_set))
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{
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VCD_enabled = 1;
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cout << "* Enabling VCD trace";
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if (dump_start_delay)
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cout << ", on at time " << dump_start.to_string();
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if (dump_stop_set)
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cout << ", off at time " << dump_stop.to_string();
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cout << endl;
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}
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// Connect up ORPSoC
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// Connect up ORPSoC
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orpsoc->clk_pad_i (clk);
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orpsoc->clk_pad_i (clk);
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orpsoc->rst_pad_i (rstn);
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orpsoc->rst_pad_i (rstn);
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orpsoc->rst_pad_o (rst_o);
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orpsoc->rst_pad_o (rst_o);
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Line 256... |
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orpsoc->gpio_a_pad_io (gpio_a); // GPIO bus - output only in
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orpsoc->gpio_a_pad_io (gpio_a); // GPIO bus - output only in
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// verilator sims
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// verilator sims
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// Connect up the VCD trace handler
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// Connect up the VCD trace handler
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trace->clk (clk); // Trace
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//trace->clk (clk); // Trace
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// Connect up the SystemC modules
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// Connect up the SystemC modules
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reset->clk (clk); // Reset
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reset->clk (clk); // Reset
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reset->rst (rst);
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reset->rst (rst);
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reset->rstn (rstn);
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reset->rstn (rstn);
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Line 278... |
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spi_sd_miso = 0; // Tie off master-in/slave-out of SD SPI bus
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spi_sd_miso = 0; // Tie off master-in/slave-out of SD SPI bus
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spi1_miso = 0;
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spi1_miso = 0;
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printf("Beginning test\n");
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//#if VM_TRACE
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if (VCD_enabled)
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{
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Verilated::traceEverOn (true);
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printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
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// Establish a new trace with its correct time resolution, and trace to
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// great depth.
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spTraceFile = new SpTraceVcdCFile ();
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//spTraceFile->spTrace()->set_time_resolution (sc_get_time_resolution());
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//setSpTimeResolution (sc_get_time_resolution ());
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//traceTarget->trace (spTraceFile, 99);
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orpsoc->trace (spTraceFile, dump_depth);
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if (dumping_now)
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{
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spTraceFile->open (vcdDumpFile.c_str());
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}
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//#endif
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}
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printf("* Beginning test\n");
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// Init the UART function
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// Init the UART function
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uart->initUart(25000000, 115200);
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uart->initUart(25000000, 115200);
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// Turn on logging by setting the "-log logfilename" option on the command line
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SIM_RUNNING = 1;
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monitor->init_displayState(argc, argv);
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// First check how we should run the sim.
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if (VCD_enabled || finish_time_set)
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{ // We'll run sim with step
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if (!VCD_enabled && finish_time_set)
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{
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// We just run the sim until the set finish time
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sc_start((double)(finish_time.to_double()), TIMESCALE_UNIT);
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SIM_RUNNING=0;
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sc_stop();
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// Print performance summary
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monitor->perfSummary();
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}
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else
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{
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if (dump_start_delay)
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{
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// Run the sim until we want to dump
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sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
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// Open the trace file
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spTraceFile->open (vcdDumpFile.c_str());
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dumping_now = 1;
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}
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if (dumping_now)
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{
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// Step the sim and generate the trace
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// Execute until we stop
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// Execute until we stop
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while(!Verilated::gotFinish())
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{
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if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
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sc_start (1,TIMESCALE_UNIT); // Step the sim
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else
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{
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spTraceFile->close();
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break;
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}
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spTraceFile->dump (sc_time_stamp().to_double());
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if (dump_stop_set)
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{
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if (sc_time_stamp() >= dump_stop)
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{
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// Close dump file
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spTraceFile->close();
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// Now continue on again until the end
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if (!finish_time_set)
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sc_start ();
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sc_start ();
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else
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{
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// Determine how long we should run for
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sc_time sim_time_remaining =
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finish_time - sc_time_stamp();
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sc_start((double)(sim_time_remaining.to_double()),
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TIMESCALE_UNIT);
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// Officially stop the sim
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sc_stop();
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// Print performance summary
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monitor->perfSummary();
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}
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break;
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}
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}
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if (finish_time_set)
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{
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if (sc_time_stamp() >= finish_time)
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{
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// Officially stop the sim
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sc_stop();
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// Close dump file
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spTraceFile->close();
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// Print performance summary
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monitor->perfSummary();
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break;
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}
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}
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}
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}
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}
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}
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else
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{
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// Simple run case
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sc_start();
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}
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// Free memory
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// Free memory
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delete monitor;
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delete monitor;
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delete reset;
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delete reset;
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delete accessor;
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delete accessor;
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delete trace;
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//delete trace;
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delete orpsoc;
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delete orpsoc;
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return 0;
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return 0;
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} /* sc_main() */
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} /* sc_main() */
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