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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Diff between revs 64 and 70

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Rev 64 Rev 70
Line 46... Line 46...
 
 
#include "Vorpsoc_top.h"
#include "Vorpsoc_top.h"
#include "OrpsocAccess.h"
#include "OrpsocAccess.h"
#include "MemoryLoad.h"
#include "MemoryLoad.h"
 
 
#include <SpTraceVcdC.h>
#include <verilated_vcd_c.h>
 
 
#include "ResetSC.h"
#include "ResetSC.h"
#include "Or1200MonitorSC.h"
#include "Or1200MonitorSC.h"
#include "GdbServerSC.h"
#include "GdbServerSC.h"
#include "UartSC.h"
#include "UartSC.h"
Line 102... Line 102...
  bool dump_start_delay_set = false, dump_stop_set = false;
  bool dump_start_delay_set = false, dump_stop_set = false;
  bool dumping_now = false;
  bool dumping_now = false;
  int dump_depth = 99; // Default dump depth
  int dump_depth = 99; // Default dump depth
  sc_time dump_start,dump_stop, finish_time;
  sc_time dump_start,dump_stop, finish_time;
  bool finish_time_set = false; // By default we will let the simulation finish naturally
  bool finish_time_set = false; // By default we will let the simulation finish naturally
  SpTraceVcdCFile *spTraceFile;
  VerilatedVcdC *verilatorVCDFile;
 
 
  /*int*/double time_val;
  /*int*/double time_val;
  bool vcd_file_name_given = false;
  bool vcd_file_name_given = false;
 
 
  bool rsp_server_enabled = false;
  bool rsp_server_enabled = false;
Line 332... Line 332...
 
 
      printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
      printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
 
 
      // Establish a new trace with its correct time resolution, and trace to
      // Establish a new trace with its correct time resolution, and trace to
      // great depth.
      // great depth.
      spTraceFile = new SpTraceVcdCFile ();
      verilatorVCDFile = new VerilatedVcdC ();
      //spTraceFile->spTrace()->set_time_resolution (sc_get_time_resolution());
      //verilatorVCDFile->verilated()->set_time_resolution (sc_get_time_resolution());
      //setSpTimeResolution (sc_get_time_resolution ());
      //setSpTimeResolution (sc_get_time_resolution ());
      //traceTarget->trace (spTraceFile, 99);
      //traceTarget->trace (verilatorVCDFile, 99);
      orpsoc->trace (spTraceFile, dump_depth);
      orpsoc->trace (verilatorVCDFile, dump_depth);
 
 
      if (dumping_now)
      if (dumping_now)
        {
        {
          spTraceFile->open (vcdDumpFile.c_str());
          verilatorVCDFile->open (vcdDumpFile.c_str());
        }
        }
    }
    }
 
 
  //printf("* Beginning test\n");
  //printf("* Beginning test\n");
 
 
Line 386... Line 386...
          if (dump_start_delay_set)
          if (dump_start_delay_set)
            {
            {
              // Run the sim until we want to dump
              // Run the sim until we want to dump
              sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
              sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
              // Open the trace file
              // Open the trace file
              spTraceFile->open (vcdDumpFile.c_str());
              verilatorVCDFile->open (vcdDumpFile.c_str());
              dumping_now = 1;
              dumping_now = 1;
            }
            }
 
 
          if (dumping_now)
          if (dumping_now)
            {
            {
Line 400... Line 400...
                {
                {
                  if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
                  if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
                    sc_start (1,TIMESCALE_UNIT); // Step the sim
                    sc_start (1,TIMESCALE_UNIT); // Step the sim
                  else
                  else
                    {
                    {
                      spTraceFile->close();
                      verilatorVCDFile->close();
                      break;
                      break;
                    }
                    }
 
 
                  spTraceFile->dump (sc_time_stamp().to_double());
                  verilatorVCDFile->dump (sc_time_stamp().to_double());
 
 
                  if (dump_stop_set)
                  if (dump_stop_set)
                    {
                    {
                      if (sc_time_stamp() >=  dump_stop)
                      if (sc_time_stamp() >=  dump_stop)
                        {
                        {
                          // Close dump file
                          // Close dump file
                          spTraceFile->close();
                          verilatorVCDFile->close();
                          // Now continue on again until the end
                          // Now continue on again until the end
                          if (!finish_time_set)
                          if (!finish_time_set)
                            sc_start();
                            sc_start();
                          else
                          else
                            {
                            {
Line 439... Line 439...
                      if (sc_time_stamp() >=  finish_time)
                      if (sc_time_stamp() >=  finish_time)
                        {
                        {
                          // Officially stop the sim
                          // Officially stop the sim
                          sc_stop();
                          sc_stop();
                          // Close dump file
                          // Close dump file
                          spTraceFile->close();
                          verilatorVCDFile->close();
                          // Do memdump if enabled
                          // Do memdump if enabled
                          monitor->memdump();
                          monitor->memdump();
                          // Print performance summary
                          // Print performance summary
                          monitor->perfSummary();
                          monitor->perfSummary();
                          break;
                          break;

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