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Line 42... |
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#include "OrpsocMain.h"
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#include "OrpsocMain.h"
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// TODO - copy orpsoc-defines.h and or1200-defines.h somewhere this can see
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// TODO - copy orpsoc-defines.h and or1200-defines.h somewhere this can see
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// them and include/exclude RSP stuff. For now is defined
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// them and include/exclude RSP stuff. For now is defined
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//#define JTAG_DEBUG
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#include "Vorpsoc_top.h"
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#include "Vorpsoc_top.h"
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#include "OrpsocAccess.h"
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#include "OrpsocAccess.h"
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#include "MemoryLoad.h"
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#include "MemoryLoad.h"
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#include <verilated_vcd_c.h>
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#include <verilated_vcd_c.h>
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#include "ResetSC.h"
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#include "ResetSC.h"
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#include "Or1200MonitorSC.h"
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#include "Or1200MonitorSC.h"
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// Include Verilog ORPSoC defines file, converted to C include format to be
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// able to detect if the debug unit is to be built in or not.
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#include "orpsoc-defines.h"
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#ifdef JTAG_DEBUG
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#ifdef JTAG_DEBUG
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# include "GdbServerSC.h"
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# include "GdbServerSC.h"
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# include "JtagSC_includes.h"
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# include "JtagSC_includes.h"
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#endif
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#endif
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#ifdef UART0
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#include "UartSC.h"
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#include "UartSC.h"
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#endif
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int SIM_RUNNING;
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int SIM_RUNNING;
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int sc_main (int argc,
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int sc_main (int argc,
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char *argv[] )
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char *argv[] )
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{
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{
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Line 90... |
sc_signal<bool> jtag_tdo;
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sc_signal<bool> jtag_tdo;
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sc_signal<bool> jtag_tms;
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sc_signal<bool> jtag_tms;
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sc_signal<bool> jtag_trst;
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sc_signal<bool> jtag_trst;
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#endif
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#endif
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#ifdef UART0
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sc_signal<bool> uart_rx; // External UART
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sc_signal<bool> uart_rx; // External UART
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sc_signal<bool> uart_tx;
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sc_signal<bool> uart_tx;
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#endif
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SIM_RUNNING = 0;
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SIM_RUNNING = 0;
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// Are we running "quiet"?
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bool quiet = false;
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// Setup the name of the VCD dump file
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// Setup the name of the VCD dump file
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bool VCD_enabled = false;
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bool VCD_enabled = false;
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string dumpNameDefault("vlt-dump.vcd");
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string dumpNameDefault("vlt-dump.vcd");
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string testNameString;
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string testNameString;
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string vcdDumpFile;
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string vcdDumpFile;
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Line 143... |
#ifdef JTAG_DEBUG
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#ifdef JTAG_DEBUG
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JtagSC *jtag; // Generate JTAG signals
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JtagSC *jtag; // Generate JTAG signals
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GdbServerSC *gdbServer; // Map RSP requests to debug unit
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GdbServerSC *gdbServer; // Map RSP requests to debug unit
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#endif
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#endif
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#ifdef UART0
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UartSC *uart; // Handle UART signals
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UartSC *uart; // Handle UART signals
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#endif
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// Instantiate the Verilator model, VCD trace handler and accessor
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// Instantiate the Verilator model, VCD trace handler and accessor
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orpsoc = new Vorpsoc_top ("orpsoc");
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orpsoc = new Vorpsoc_top ("orpsoc");
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accessor = new OrpsocAccess (orpsoc);
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accessor = new OrpsocAccess (orpsoc);
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Line 164... |
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#ifdef JTAG_DEBUG
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#ifdef JTAG_DEBUG
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jtag = new JtagSC ("jtag");
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jtag = new JtagSC ("jtag");
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#endif
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#endif
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uart = new UartSC("uart"); // TODO: Probalby some sort of param
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#ifdef UART0
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uart = new UartSC("uart");
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#endif
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// Parse command line options
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// Parse command line options
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// Default is for VCD generation OFF, only turned on if specified on command
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// Default is for VCD generation OFF, only turned on if specified on command
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// line
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// line
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time_val = strtod(argv[i+1],NULL);
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time_val = strtod(argv[i+1],NULL);
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sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
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sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
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dump_stop = dump_stop_time;
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dump_stop = dump_stop_time;
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dump_stop_set = true;
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dump_stop_set = true;
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}
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}
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/*
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Depth setting of VCD doesn't appear to work, I think it's only
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configurable during at compile time .
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*/
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/* else if ( (strcmp(argv[i], "-p")==0) ||
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(strcmp(argv[i], "--vcddepth")==0) )
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{
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dump_depth = atoi(argv[i+1]);
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}*/
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#ifdef JTAG_DEBUG
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#ifdef JTAG_DEBUG
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else if ( (strcmp(argv[i], "-r")==0) ||
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else if ( (strcmp(argv[i], "-r")==0) ||
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(strcmp(argv[i], "--rsp")==0) )
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(strcmp(argv[i], "--rsp")==0) )
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{
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{
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rsp_server_enabled = true;
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rsp_server_enabled = true;
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rsp_server_port = atoi(argv[i+1]);
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rsp_server_port = atoi(argv[i+1]);
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i++;
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i++;
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}
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}
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}
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}
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#endif
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#endif
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/*
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else if ((strcmp(argv[i], "-q")==0) ||
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Depth setting of VCD doesn't appear to work, I think it's only
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(strcmp(argv[i], "--quiet")==0))
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configurable during at compile time .
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{
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*/
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quiet = true;
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/* else if ( (strcmp(argv[i], "-p")==0) ||
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}
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(strcmp(argv[i], "--vcddepth")==0) )
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{
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dump_depth = atoi(argv[i+1]);
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}*/
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else if ( (strcmp(argv[i], "-h")==0) ||
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else if ( (strcmp(argv[i], "-h")==0) ||
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(strcmp(argv[i], "--help")==0) )
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(strcmp(argv[i], "--help")==0) )
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{
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{
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printf("Usage: %s [options]\n",argv[0]);
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printf("Usage: %s [options]\n",argv[0]);
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printf("\n ORPSoCv2 cycle accurate model\n");
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printf("\n ORPSoCv2 cycle accurate model\n");
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printf(" For details visit http://opencores.org/openrisc,orpsocv2\n");
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printf(" For details visit http://opencores.org/openrisc,orpsocv2\n");
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printf("\n");
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printf("\n");
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printf("Options:\n");
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printf("Options:\n");
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printf(" -h, --help\t\tPrint this help message\n");
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printf(" -h, --help\t\tPrint this help message\n");
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printf(" -q, --quiet\t\tDisable all except UART print out\n");
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printf("\nSimulation control:\n");
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printf("\nSimulation control:\n");
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printf(" -f, --program <file> \tLoad program from OR32 ELF <file>\n");
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printf(" -f, --program <file> \tLoad program from OR32 ELF <file>\n");
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printf(" -e, --endtime <val> \tStop the sim at <val> ns\n");
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printf(" -e, --endtime <val> \tStop the sim at <val> ns\n");
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printf("\nVCD generation:\n");
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printf("\nVCD generation:\n");
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printf(" -v, --vcdon\t\tEnable VCD generation\n");
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printf(" -v, --vcdon\t\tEnable VCD generation\n");
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Line 317... |
orpsoc->tdi_pad_i (jtag_tdi);
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orpsoc->tdi_pad_i (jtag_tdi);
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orpsoc->tms_pad_i (jtag_tms);
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orpsoc->tms_pad_i (jtag_tms);
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orpsoc->tdo_pad_o (jtag_tdo);
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orpsoc->tdo_pad_o (jtag_tdo);
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#endif
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#endif
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#ifdef UART0
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orpsoc->uart0_srx_pad_i (uart_rx); // External UART
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orpsoc->uart0_srx_pad_i (uart_rx); // External UART
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orpsoc->uart0_stx_pad_o (uart_tx);
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orpsoc->uart0_stx_pad_o (uart_tx);
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#endif
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// Connect up the SystemC modules
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// Connect up the SystemC modules
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reset->clk (clk); // Reset
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reset->clk (clk); // Reset
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reset->rst (rst);
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reset->rst (rst);
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reset->rstn (rstn);
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reset->rstn (rstn);
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Line 338... |
jtag->tdo (jtag_tdo);
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jtag->tdo (jtag_tdo);
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jtag->tms (jtag_tms);
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jtag->tms (jtag_tms);
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jtag->trst (jtag_trst);
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jtag->trst (jtag_trst);
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#endif
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#endif
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#ifdef UART0
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uart->clk (clk); // Uart
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uart->clk (clk); // Uart
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uart->uartrx (uart_rx); // orpsoc's receive line
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uart->uartrx (uart_rx); // orpsoc's receive line
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uart->uarttx (uart_tx); // orpsoc's transmit line
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uart->uarttx (uart_tx); // orpsoc's transmit line
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#endif
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// Tie off signals
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// Tie off signals
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#ifdef JTAG_DEBUG
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#ifdef JTAG_DEBUG
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jtag_tdi = 1; // Tie off the JTAG inputs
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jtag_tdi = 1; // Tie off the JTAG inputs
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jtag_tms = 1;
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jtag_tms = 1;
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Line 370... |
}
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}
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}
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}
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//printf("* Beginning test\n");
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//printf("* Beginning test\n");
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#ifdef UART0
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// Init the UART function
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// Init the UART function
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uart->initUart(50000000, 115200);
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uart->initUart(50000000, 115200);
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#endif
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if (do_program_file_load) // Did the user specify a file to load?
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if (do_program_file_load) // Did the user specify a file to load?
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{
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{
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cout << "* Loading program from " << program_file << endl;
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cout << "* Loading program from " << program_file << endl;
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if (memoryload->loadcode(program_file,0,0) < 0)
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if (memoryload->loadcode(program_file,0,0) < 0)
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{
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{
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cout << "* Error: executable file " << program_file <<
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cout << "* Error: executable file " << program_file <<
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" not loaded" << endl;
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" not loaded" << endl;
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}
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}
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}
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}
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else // Load SRAM from VMEM file
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else // No ELF file specified, default is to load SRAM from VMEM file
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{
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{
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if (!quiet)
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cout << "* Loading memory with image from default file, sram.vmem"
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<< endl;
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accessor->do_ram_readmemh();
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accessor->do_ram_readmemh();
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}
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}
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SIM_RUNNING = 1;
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SIM_RUNNING = 1;
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