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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Diff between revs 363 and 397

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Rev 363 Rev 397
Line 42... Line 42...
 
 
#include "OrpsocMain.h"
#include "OrpsocMain.h"
 
 
// TODO - copy orpsoc-defines.h and or1200-defines.h somewhere this can see
// TODO - copy orpsoc-defines.h and or1200-defines.h somewhere this can see
//        them and include/exclude RSP stuff. For now is defined
//        them and include/exclude RSP stuff. For now is defined
//#define JTAG_DEBUG
 
 
 
#include "Vorpsoc_top.h"
#include "Vorpsoc_top.h"
#include "OrpsocAccess.h"
#include "OrpsocAccess.h"
#include "MemoryLoad.h"
#include "MemoryLoad.h"
 
 
#include <verilated_vcd_c.h>
#include <verilated_vcd_c.h>
 
 
#include "ResetSC.h"
#include "ResetSC.h"
#include "Or1200MonitorSC.h"
#include "Or1200MonitorSC.h"
 
 
 
 
 
// Include Verilog ORPSoC defines file, converted to C include format to be
 
// able to detect if the debug unit is to be built in or not.
 
#include "orpsoc-defines.h"
 
 
 
 
#ifdef JTAG_DEBUG
#ifdef JTAG_DEBUG
# include "GdbServerSC.h"
# include "GdbServerSC.h"
# include "JtagSC_includes.h"
# include "JtagSC_includes.h"
#endif
#endif
 
 
 
#ifdef UART0
#include "UartSC.h"
#include "UartSC.h"
 
#endif
 
 
int SIM_RUNNING;
int SIM_RUNNING;
int sc_main (int   argc,
int sc_main (int   argc,
             char *argv[] )
             char *argv[] )
{
{
Line 82... Line 90...
  sc_signal<bool>      jtag_tdo;
  sc_signal<bool>      jtag_tdo;
  sc_signal<bool>      jtag_tms;
  sc_signal<bool>      jtag_tms;
  sc_signal<bool>      jtag_trst;
  sc_signal<bool>      jtag_trst;
#endif
#endif
 
 
 
#ifdef UART0
  sc_signal<bool>      uart_rx;         // External UART
  sc_signal<bool>      uart_rx;         // External UART
  sc_signal<bool>      uart_tx;
  sc_signal<bool>      uart_tx;
 
#endif
 
 
  SIM_RUNNING = 0;
  SIM_RUNNING = 0;
 
 
 
  // Are we running "quiet"?
 
  bool quiet = false;
  // Setup the name of the VCD dump file
  // Setup the name of the VCD dump file
  bool VCD_enabled = false;
  bool VCD_enabled = false;
  string dumpNameDefault("vlt-dump.vcd");
  string dumpNameDefault("vlt-dump.vcd");
  string testNameString;
  string testNameString;
  string vcdDumpFile;
  string vcdDumpFile;
Line 131... Line 143...
#ifdef JTAG_DEBUG
#ifdef JTAG_DEBUG
  JtagSC           *jtag;               // Generate JTAG signals
  JtagSC           *jtag;               // Generate JTAG signals
  GdbServerSC      *gdbServer;          // Map RSP requests to debug unit
  GdbServerSC      *gdbServer;          // Map RSP requests to debug unit
#endif
#endif
 
 
 
#ifdef UART0
  UartSC          *uart;                // Handle UART signals
  UartSC          *uart;                // Handle UART signals
 
#endif
 
 
  // Instantiate the Verilator model, VCD trace handler and accessor
  // Instantiate the Verilator model, VCD trace handler and accessor
  orpsoc     = new Vorpsoc_top ("orpsoc");
  orpsoc     = new Vorpsoc_top ("orpsoc");
 
 
  accessor   = new OrpsocAccess (orpsoc);
  accessor   = new OrpsocAccess (orpsoc);
Line 150... Line 164...
 
 
#ifdef JTAG_DEBUG  
#ifdef JTAG_DEBUG  
  jtag          = new JtagSC ("jtag");
  jtag          = new JtagSC ("jtag");
#endif
#endif
 
 
  uart          = new UartSC("uart"); // TODO: Probalby some sort of param
#ifdef UART0
 
  uart          = new UartSC("uart");
 
#endif
 
 
  // Parse command line options
  // Parse command line options
  // Default is for VCD generation OFF, only turned on if specified on command 
  // Default is for VCD generation OFF, only turned on if specified on command 
  // line
  // line
 
 
Line 212... Line 228...
              time_val = strtod(argv[i+1],NULL);
              time_val = strtod(argv[i+1],NULL);
              sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
              sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
              dump_stop = dump_stop_time;
              dump_stop = dump_stop_time;
              dump_stop_set = true;
              dump_stop_set = true;
            }
            }
 
          /*
 
             Depth setting of VCD doesn't appear to work, I think it's only
 
             configurable during at compile time .
 
          */
 
          /*      else if ( (strcmp(argv[i], "-p")==0) ||
 
                  (strcmp(argv[i], "--vcddepth")==0) )
 
                  {
 
                  dump_depth = atoi(argv[i+1]);
 
          }*/
#ifdef JTAG_DEBUG
#ifdef JTAG_DEBUG
          else if ( (strcmp(argv[i], "-r")==0) ||
          else if ( (strcmp(argv[i], "-r")==0) ||
                    (strcmp(argv[i], "--rsp")==0) )
                    (strcmp(argv[i], "--rsp")==0) )
            {
            {
              rsp_server_enabled = true;
              rsp_server_enabled = true;
Line 224... Line 249...
                                  rsp_server_port = atoi(argv[i+1]);
                                  rsp_server_port = atoi(argv[i+1]);
                                  i++;
                                  i++;
                                }
                                }
            }
            }
#endif
#endif
          /*
          else if ((strcmp(argv[i], "-q")==0) ||
             Depth setting of VCD doesn't appear to work, I think it's only
                   (strcmp(argv[i], "--quiet")==0))
             configurable during at compile time .
            {
          */
              quiet = true;
          /*      else if ( (strcmp(argv[i], "-p")==0) ||
            }
                  (strcmp(argv[i], "--vcddepth")==0) )
 
                  {
 
                  dump_depth = atoi(argv[i+1]);
 
                  }*/
 
          else if ( (strcmp(argv[i], "-h")==0) ||
          else if ( (strcmp(argv[i], "-h")==0) ||
                    (strcmp(argv[i], "--help")==0) )
                    (strcmp(argv[i], "--help")==0) )
            {
            {
              printf("Usage: %s [options]\n",argv[0]);
              printf("Usage: %s [options]\n",argv[0]);
              printf("\n  ORPSoCv2 cycle accurate model\n");
              printf("\n  ORPSoCv2 cycle accurate model\n");
              printf("  For details visit http://opencores.org/openrisc,orpsocv2\n");
              printf("  For details visit http://opencores.org/openrisc,orpsocv2\n");
              printf("\n");
              printf("\n");
              printf("Options:\n");
              printf("Options:\n");
              printf("  -h, --help\t\tPrint this help message\n");
              printf("  -h, --help\t\tPrint this help message\n");
 
              printf("  -q, --quiet\t\tDisable all except UART print out\n");
              printf("\nSimulation control:\n");
              printf("\nSimulation control:\n");
              printf("  -f, --program <file> \tLoad program from OR32 ELF <file>\n");
              printf("  -f, --program <file> \tLoad program from OR32 ELF <file>\n");
              printf("  -e, --endtime <val> \tStop the sim at <val> ns\n");
              printf("  -e, --endtime <val> \tStop the sim at <val> ns\n");
              printf("\nVCD generation:\n");
              printf("\nVCD generation:\n");
              printf("  -v, --vcdon\t\tEnable VCD generation\n");
              printf("  -v, --vcdon\t\tEnable VCD generation\n");
Line 295... Line 317...
  orpsoc->tdi_pad_i  (jtag_tdi);
  orpsoc->tdi_pad_i  (jtag_tdi);
  orpsoc->tms_pad_i  (jtag_tms);
  orpsoc->tms_pad_i  (jtag_tms);
  orpsoc->tdo_pad_o  (jtag_tdo);
  orpsoc->tdo_pad_o  (jtag_tdo);
#endif
#endif
 
 
 
#ifdef UART0
  orpsoc->uart0_srx_pad_i (uart_rx);            // External UART
  orpsoc->uart0_srx_pad_i (uart_rx);            // External UART
  orpsoc->uart0_stx_pad_o (uart_tx);
  orpsoc->uart0_stx_pad_o (uart_tx);
 
#endif
 
 
  // Connect up the SystemC  modules
  // Connect up the SystemC  modules
  reset->clk (clk);                     // Reset
  reset->clk (clk);                     // Reset
  reset->rst (rst);
  reset->rst (rst);
  reset->rstn (rstn);
  reset->rstn (rstn);
Line 314... Line 338...
  jtag->tdo (jtag_tdo);
  jtag->tdo (jtag_tdo);
  jtag->tms (jtag_tms);
  jtag->tms (jtag_tms);
  jtag->trst (jtag_trst);
  jtag->trst (jtag_trst);
#endif
#endif
 
 
 
#ifdef UART0
  uart->clk (clk); // Uart
  uart->clk (clk); // Uart
  uart->uartrx (uart_rx); // orpsoc's receive line
  uart->uartrx (uart_rx); // orpsoc's receive line
  uart->uarttx (uart_tx); // orpsoc's transmit line
  uart->uarttx (uart_tx); // orpsoc's transmit line
 
#endif
 
 
  // Tie off signals
  // Tie off signals
#ifdef JTAG_DEBUG
#ifdef JTAG_DEBUG
  jtag_tdi      = 1;                    // Tie off the JTAG inputs
  jtag_tdi      = 1;                    // Tie off the JTAG inputs
  jtag_tms      = 1;
  jtag_tms      = 1;
Line 344... Line 370...
        }
        }
    }
    }
 
 
  //printf("* Beginning test\n");
  //printf("* Beginning test\n");
 
 
 
#ifdef UART0
  // Init the UART function
  // Init the UART function
  uart->initUart(50000000, 115200);
  uart->initUart(50000000, 115200);
 
#endif
 
 
  if (do_program_file_load) // Did the user specify a file to load?
  if (do_program_file_load) // Did the user specify a file to load?
    {
    {
      cout << "* Loading program from " << program_file << endl;
      cout << "* Loading program from " << program_file << endl;
      if (memoryload->loadcode(program_file,0,0) < 0)
      if (memoryload->loadcode(program_file,0,0) < 0)
        {
        {
          cout << "* Error: executable file " << program_file <<
          cout << "* Error: executable file " << program_file <<
            " not loaded" << endl;
            " not loaded" << endl;
        }
        }
    }
    }
  else // Load SRAM from VMEM file
  else // No ELF file specified, default is to load SRAM from VMEM file
    {
    {
 
      if (!quiet)
 
        cout << "* Loading memory with image from default file, sram.vmem"
 
             << endl;
      accessor->do_ram_readmemh();
      accessor->do_ram_readmemh();
    }
    }
 
 
  SIM_RUNNING = 1;
  SIM_RUNNING = 1;
 
 

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