| Line 1304... |
Line 1304... |
begin
|
begin
|
smii_rx_dat_addr = start_addr;
|
smii_rx_dat_addr = start_addr;
|
smii_rx_len = len;
|
smii_rx_len = len;
|
smii_rx_go = 1;
|
smii_rx_go = 1;
|
|
|
send_mii_rx_packet(preamble_data, preamble_len, sfd_data, start_addr, len, plus_drible_nibble,
|
send_mii_rx_packet(preamble_data, preamble_len, sfd_data, start_addr,
|
assert_rx_err);
|
len, plus_drible_nibble, assert_rx_err);
|
|
`ifdef SMII0
|
while(smii_rx_go)
|
while(smii_rx_go)
|
@(posedge smii_clk_i);
|
@(posedge smii_clk_i);
|
|
`endif
|
|
|
end
|
end
|
endtask // send_rx_packet
|
endtask // send_rx_packet
|
|
|
task send_mii_rx_packet;
|
task send_mii_rx_packet;
|
| Line 1345... |
Line 1347... |
`endif
|
`endif
|
// set initial rx memory address
|
// set initial rx memory address
|
rx_mem_addr_in = start_addr;
|
rx_mem_addr_in = start_addr;
|
|
|
// send preamble
|
// send preamble
|
for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
|
for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16);
|
|
rx_cnt = rx_cnt + 1)
|
begin
|
begin
|
#1 mrxd_o = preamble_data[3:0];
|
#1 mrxd_o = preamble_data[3:0];
|
#1 preamble_data = preamble_data >> 4;
|
#1 preamble_data = preamble_data >> 4;
|
@(posedge mrx_clk_o);
|
@(posedge mrx_clk_o);
|
end
|
end
|
| Line 1371... |
Line 1374... |
rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
|
rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
|
mrxd_o = rx_mem_data_out[3:0];
|
mrxd_o = rx_mem_data_out[3:0];
|
@(posedge mrx_clk_o);
|
@(posedge mrx_clk_o);
|
#1;
|
#1;
|
|
|
// Assert error if told to .... TODO: make this occur at random time
|
// Assert error if told to .... TODO: make this occur at random
|
// jb
|
// time - JPB
|
|
|
if (rx_cnt > 18) rx_err(assert_rx_err);
|
if (rx_cnt > 18) rx_err(assert_rx_err);
|
|
|
mrxd_o = rx_mem_data_out[7:4];
|
mrxd_o = rx_mem_data_out[7:4];
|
rx_mem_addr_in = rx_mem_addr_in + 1;
|
rx_mem_addr_in = rx_mem_addr_in + 1;
|
@(posedge mrx_clk_o);
|
@(posedge mrx_clk_o);
|
