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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [mt48lc16m16a2.v] - Diff between revs 403 and 495

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Rev 403 Rev 495
Line 51... Line 51...
 
 
`ifdef MT48LC32M16
`ifdef MT48LC32M16
   // Params. for  mt48lc32m16a2 (64MB part)
   // Params. for  mt48lc32m16a2 (64MB part)
   parameter addr_bits =      13;
   parameter addr_bits =      13;
   parameter col_bits  =      10;
   parameter col_bits  =      10;
   parameter mem_sizes = 8388606;
   parameter mem_sizes = 8388608;
`endif
`endif
 
 
`ifdef MT48LC16M16
`ifdef MT48LC16M16
   // Params. for  mt48lc16m16a2 (32MB part)
   // Params. for  mt48lc16m16a2 (32MB part)
   parameter addr_bits =      13;
   parameter addr_bits =      13;
   parameter col_bits  =       9;
   parameter col_bits  =       9;
   parameter mem_sizes = 4194303;
   parameter mem_sizes = 4194304;
`endif
`endif
 
 
`ifdef MT48LC4M16
`ifdef MT48LC4M16
  //Params for mt48lc4m16a2 (8MB part)
  //Params for mt48lc4m16a2 (8MB part)
   parameter addr_bits =      12;
   parameter addr_bits =      12;
   parameter col_bits  =       8;
   parameter col_bits  =       8;
   parameter mem_sizes =   1048575;
   parameter mem_sizes =   1048576;
`endif
`endif
 
 
   // Common to all parts
   // Common to all parts
   parameter data_bits =      16;
   parameter data_bits =      16;
 
 
 
 
 
 
    inout     [data_bits - 1 : 0] Dq;
    inout     [data_bits - 1 : 0] Dq;
    input [addr_bits - 1 : 0]      Addr;
    input [addr_bits - 1 : 0]      Addr;
    input                 [1 : 0] Ba;
    input                 [1 : 0] Ba;
    input                         Clk;
    input                         Clk;
    input                         Cke;
    input                         Cke;
Line 1150... Line 1148...
           data = short[15:8];
           data = short[15:8];
         else
         else
           data = short[7:0];
           data = short[7:0];
 
 
         //$display("SDRAM addr 0x%0h, bank %0d, short 0x%0h, byte 0x%0h", addr, bank, short, data);
         //$display("SDRAM addr 0x%0h, bank %0d, short 0x%0h, byte 0x%0h", addr, bank, short, data);
 
      end
 
   endtask // get_byte
 
 
 
   task set_byte;
 
      input [31:0] addr;
 
      input [7:0] data;
 
      reg [1:0]     bank;
 
      reg [15:0]   short;
 
 
 
      begin
 
         bank = addr[24:23];
 
 
 
         case(bank)
 
           2'b00:
 
             short = Bank0[addr[22:1]];
 
           2'b01:
 
             short = Bank1[addr[22:1]];
 
           2'b10:
 
             short = Bank2[addr[22:1]];
 
           2'b11:
 
             short = Bank3[addr[22:1]];
 
         endcase // case (bank)
 
 
 
         // set the byte in the short
 
         if (!addr[0])
 
           short[15:8] = data;
 
         else
 
           short[7:0] = data;
 
 
 
         // Write short back to memory
 
         case(bank)
 
           2'b00:
 
             Bank0[addr[22:1]] = short;
 
           2'b01:
 
             Bank1[addr[22:1]] = short;
 
           2'b10:
 
             Bank2[addr[22:1]] = short;
 
           2'b11:
 
             Bank3[addr[22:1]] = short;
 
         endcase // case (bank)
 
 
      end
      end
   endtask // get_byte
   endtask // set_byte
 
 
 
   task get_short;
 
      input [31:0] addr;
 
      output [15:0] data;
 
      reg [1:0]     bank;
 
      reg [15:0]   short;
 
 
 
      begin
 
         bank = addr[24:23];
 
 
 
         case(bank)
 
           2'b00:
 
             short = Bank0[addr[22:1]];
 
           2'b01:
 
             short = Bank1[addr[22:1]];
 
           2'b10:
 
             short = Bank2[addr[22:1]];
 
           2'b11:
 
             short = Bank3[addr[22:1]];
 
         endcase // case (bank)
 
 
 
         data = short;
 
      end
 
   endtask // get_short
 
 
 
   task set_short;
 
      input [31:0] addr;
 
      input [15:0] data;
 
      reg [1:0]     bank;
 
      begin
 
         bank = addr[24:23];
 
 
 
         // Write short back to memory
 
         case(bank)
 
           2'b00:
 
             Bank0[addr[22:1]] = data;
 
           2'b01:
 
             Bank1[addr[22:1]] = data;
 
           2'b10:
 
             Bank2[addr[22:1]] = data;
 
           2'b11:
 
             Bank3[addr[22:1]] = data;
 
         endcase // case (bank)
 
      end
 
   endtask // set_short
 
 
endmodule
endmodule
 
 
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