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Line 51... |
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`ifdef MT48LC32M16
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`ifdef MT48LC32M16
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// Params. for mt48lc32m16a2 (64MB part)
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// Params. for mt48lc32m16a2 (64MB part)
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parameter addr_bits = 13;
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parameter addr_bits = 13;
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parameter col_bits = 10;
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parameter col_bits = 10;
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parameter mem_sizes = 8388606;
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parameter mem_sizes = 8388608;
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`endif
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`endif
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`ifdef MT48LC16M16
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`ifdef MT48LC16M16
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// Params. for mt48lc16m16a2 (32MB part)
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// Params. for mt48lc16m16a2 (32MB part)
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parameter addr_bits = 13;
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parameter addr_bits = 13;
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parameter col_bits = 9;
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parameter col_bits = 9;
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parameter mem_sizes = 4194303;
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parameter mem_sizes = 4194304;
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`endif
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`endif
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`ifdef MT48LC4M16
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`ifdef MT48LC4M16
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//Params for mt48lc4m16a2 (8MB part)
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//Params for mt48lc4m16a2 (8MB part)
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parameter addr_bits = 12;
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parameter addr_bits = 12;
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parameter col_bits = 8;
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parameter col_bits = 8;
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parameter mem_sizes = 1048575;
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parameter mem_sizes = 1048576;
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`endif
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`endif
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// Common to all parts
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// Common to all parts
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parameter data_bits = 16;
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parameter data_bits = 16;
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inout [data_bits - 1 : 0] Dq;
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inout [data_bits - 1 : 0] Dq;
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input [addr_bits - 1 : 0] Addr;
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input [addr_bits - 1 : 0] Addr;
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input [1 : 0] Ba;
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input [1 : 0] Ba;
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input Clk;
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input Clk;
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input Cke;
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input Cke;
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Line 1148... |
data = short[15:8];
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data = short[15:8];
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else
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else
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data = short[7:0];
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data = short[7:0];
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//$display("SDRAM addr 0x%0h, bank %0d, short 0x%0h, byte 0x%0h", addr, bank, short, data);
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//$display("SDRAM addr 0x%0h, bank %0d, short 0x%0h, byte 0x%0h", addr, bank, short, data);
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end
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endtask // get_byte
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task set_byte;
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input [31:0] addr;
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input [7:0] data;
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reg [1:0] bank;
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reg [15:0] short;
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begin
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bank = addr[24:23];
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case(bank)
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2'b00:
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short = Bank0[addr[22:1]];
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2'b01:
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short = Bank1[addr[22:1]];
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2'b10:
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short = Bank2[addr[22:1]];
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2'b11:
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short = Bank3[addr[22:1]];
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endcase // case (bank)
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// set the byte in the short
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if (!addr[0])
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short[15:8] = data;
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else
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short[7:0] = data;
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// Write short back to memory
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case(bank)
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2'b00:
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Bank0[addr[22:1]] = short;
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2'b01:
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Bank1[addr[22:1]] = short;
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2'b10:
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Bank2[addr[22:1]] = short;
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2'b11:
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Bank3[addr[22:1]] = short;
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endcase // case (bank)
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end
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end
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endtask // get_byte
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endtask // set_byte
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task get_short;
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input [31:0] addr;
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output [15:0] data;
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reg [1:0] bank;
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reg [15:0] short;
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begin
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bank = addr[24:23];
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case(bank)
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2'b00:
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short = Bank0[addr[22:1]];
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2'b01:
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short = Bank1[addr[22:1]];
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2'b10:
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short = Bank2[addr[22:1]];
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2'b11:
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short = Bank3[addr[22:1]];
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endcase // case (bank)
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data = short;
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end
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endtask // get_short
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task set_short;
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input [31:0] addr;
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input [15:0] data;
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reg [1:0] bank;
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begin
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bank = addr[24:23];
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// Write short back to memory
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case(bank)
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2'b00:
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Bank0[addr[22:1]] = data;
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2'b01:
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Bank1[addr[22:1]] = data;
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2'b10:
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Bank2[addr[22:1]] = data;
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2'b11:
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Bank3[addr[22:1]] = data;
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endcase // case (bank)
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end
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endtask // set_short
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endmodule
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endmodule
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