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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [mt48lc16m16a2.v] - Diff between revs 44 and 403

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Rev 44 Rev 403
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*      Micron Technology Inc.
*      Micron Technology Inc.
*
*
**************************************************************************/
**************************************************************************/
 
 
`include "timescale.v"
`include "timescale.v"
 
`include "test-defines.v"
 
 
 
// Uncomment one of the following to have the appropriate size definitions
 
// for the part.
 
//`define MT48LC32M16   // 64MB part
 
`define MT48LC16M16   // 32MB part
 
//`define MT48LC4M16    //  8MB part
 
 
module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
 
 
 
 
 
`ifdef MT48LC32M16
 
   // Params. for  mt48lc32m16a2 (64MB part)
 
   parameter addr_bits =      13;
 
   parameter col_bits  =      10;
 
   parameter mem_sizes = 8388606;
 
`endif
 
 
 
`ifdef MT48LC16M16
 
   // Params. for  mt48lc16m16a2 (32MB part)
    parameter addr_bits =      13;
    parameter addr_bits =      13;
    parameter data_bits =      16;
 
    parameter col_bits  =       9;
    parameter col_bits  =       9;
    parameter mem_sizes = 4194303;
    parameter mem_sizes = 4194303;
 
`endif
 
 
 
`ifdef MT48LC4M16
 
  //Params for mt48lc4m16a2 (8MB part)
 
   parameter addr_bits =      12;
 
   parameter col_bits  =       8;
 
   parameter mem_sizes =   1048575;
 
`endif
 
 
 
   // Common to all parts
 
   parameter data_bits =      16;
 
 
 
 
 
 
    inout     [data_bits - 1 : 0] Dq;
    inout     [data_bits - 1 : 0] Dq;
    input     [addr_bits - 1 : 0] Addr;
    input     [addr_bits - 1 : 0] Addr;
    input                 [1 : 0] Ba;
    input                 [1 : 0] Ba;
    input                         Clk;
    input                         Clk;
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    reg       [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
 
       reg       [31 : 0] Bank0_32bit [0 : (mem_sizes/2)]; // Temporary 32-bit wide array to hold readmemh()'d data before loading into 16-bit wide array
    reg                   [1 : 0] Bank_addr [0 : 3];                // Bank Address Pipeline
    reg                   [1 : 0] Bank_addr [0 : 3];                // Bank Address Pipeline
    reg        [col_bits - 1 : 0] Col_addr [0 : 3];                 // Column Address Pipeline
    reg        [col_bits - 1 : 0] Col_addr [0 : 3];                 // Column Address Pipeline
    reg                   [3 : 0] Command [0 : 3];                  // Command Operation Pipeline
    reg                   [3 : 0] Command [0 : 3];                  // Command Operation Pipeline
    reg                   [1 : 0] Dqm_reg0, Dqm_reg1;               // DQM Operation Pipeline
    reg                   [1 : 0] Dqm_reg0, Dqm_reg1;               // DQM Operation Pipeline
    reg       [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
    reg       [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
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    time  RC_chk0, RC_chk1, RC_chk2, RC_chk3;
    time  RC_chk0, RC_chk1, RC_chk2, RC_chk3;
    time  RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
    time  RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
    time  RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
    time  RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
    time  RP_chk0, RP_chk1, RP_chk2, RP_chk3;
    time  RP_chk0, RP_chk1, RP_chk2, RP_chk3;
 
 
 
   integer mem_cnt;
 
 
 
 
    initial begin
    initial begin
        Dq_reg = {data_bits{1'bz}};
        Dq_reg = {data_bits{1'bz}};
        Data_in_enable = 0; Data_out_enable = 0;
        Data_in_enable = 0; Data_out_enable = 0;
        Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
        Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
        Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
        Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
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        RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
        RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
        RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
        RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
        RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
        RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
        RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
        RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
        $timeformat (-9, 1, " ns", 12);
        $timeformat (-9, 1, " ns", 12);
 
//`define INIT_CLEAR_MEM_BANKS       
 
`ifdef INIT_CLEAR_MEM_BANKS // Added, jb
 
       // Initialse the memory before we use it, clearing x's
 
       for(mem_cnt = 0; mem_cnt < mem_sizes; mem_cnt = mem_cnt + 1)
 
         begin
 
            Bank0[mem_cnt] = 0;
 
            Bank1[mem_cnt] = 0;
 
            Bank2[mem_cnt] = 0;
 
            Bank3[mem_cnt] = 0;
 
         end
 
`endif
 
 
 
`ifdef PRELOAD_RAM // Added jb
 
       $display("* Preloading SDRAM bank 0.\n");
 
       // Uses the vmem file for the internal SRAM, so words are 32-bits wide
 
       // and we need to copy them into the 16-bit wide array, which the simulator
 
       // can't figure out how to do, so we'll do it manually here.
 
       $readmemh("sram.vmem", Bank0_32bit);
 
       for (mem_cnt=0;mem_cnt < (mem_sizes/2); mem_cnt = mem_cnt + 1)
 
         begin
 
            Bank0[(mem_cnt*2)+1] = Bank0_32bit[mem_cnt][15:0];
 
            Bank0[(mem_cnt*2)] = Bank0_32bit[mem_cnt][31:16];
 
         end
 
`endif
    end
    end
 
 
    // System clock generator
    // System clock generator
    always begin
    always begin
        @ (posedge Clk) begin
        @ (posedge Clk) begin
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        $setuphold(posedge Clk,    Ba,    tAS,  tAH);
        $setuphold(posedge Clk,    Ba,    tAS,  tAH);
        $setuphold(posedge Clk,    Dqm,   tCMS, tCMH);
        $setuphold(posedge Clk,    Dqm,   tCMS, tCMH);
        $setuphold(posedge Dq_chk, Dq,    tDS,  tDH);
        $setuphold(posedge Dq_chk, Dq,    tDS,  tDH);
    endspecify
    endspecify
 
 
 
   task get_byte;
 
      input [31:0] addr;
 
      output [7:0] data;
 
      reg [1:0]     bank;
 
      reg [15:0]   short;
 
 
 
      begin
 
         bank = addr[24:23];
 
 
 
         case(bank)
 
           2'b00:
 
             short = Bank0[addr[22:1]];
 
           2'b01:
 
             short = Bank1[addr[22:1]];
 
           2'b10:
 
             short = Bank2[addr[22:1]];
 
           2'b11:
 
             short = Bank3[addr[22:1]];
 
         endcase // case (bank)
 
 
 
         // Get the byte from the short
 
         if (!addr[0])
 
           data = short[15:8];
 
         else
 
           data = short[7:0];
 
 
 
         //$display("SDRAM addr 0x%0h, bank %0d, short 0x%0h, byte 0x%0h", addr, bank, short, data);
 
 
 
 
 
      end
 
   endtask // get_byte
 
 
endmodule
endmodule
 
 
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