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* Micron Technology Inc.
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* Micron Technology Inc.
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*
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*
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**************************************************************************/
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**************************************************************************/
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`include "timescale.v"
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`include "timescale.v"
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`include "test-defines.v"
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// Uncomment one of the following to have the appropriate size definitions
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// for the part.
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//`define MT48LC32M16 // 64MB part
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`define MT48LC16M16 // 32MB part
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//`define MT48LC4M16 // 8MB part
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module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
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module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
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`ifdef MT48LC32M16
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// Params. for mt48lc32m16a2 (64MB part)
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parameter addr_bits = 13;
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parameter col_bits = 10;
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parameter mem_sizes = 8388606;
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`endif
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`ifdef MT48LC16M16
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// Params. for mt48lc16m16a2 (32MB part)
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parameter addr_bits = 13;
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parameter addr_bits = 13;
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parameter data_bits = 16;
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parameter col_bits = 9;
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parameter col_bits = 9;
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parameter mem_sizes = 4194303;
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parameter mem_sizes = 4194303;
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`endif
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`ifdef MT48LC4M16
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//Params for mt48lc4m16a2 (8MB part)
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parameter addr_bits = 12;
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parameter col_bits = 8;
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parameter mem_sizes = 1048575;
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`endif
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// Common to all parts
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parameter data_bits = 16;
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inout [data_bits - 1 : 0] Dq;
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inout [data_bits - 1 : 0] Dq;
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input [addr_bits - 1 : 0] Addr;
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input [addr_bits - 1 : 0] Addr;
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input [1 : 0] Ba;
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input [1 : 0] Ba;
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input Clk;
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input Clk;
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| Line 59... |
Line 88... |
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reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
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reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
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reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
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reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
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reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
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reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
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reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
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reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
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reg [31 : 0] Bank0_32bit [0 : (mem_sizes/2)]; // Temporary 32-bit wide array to hold readmemh()'d data before loading into 16-bit wide array
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reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
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reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
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reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
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reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
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reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
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reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
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reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
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reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
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reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
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reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
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time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
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time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
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time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
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time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
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time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
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time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
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time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
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time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
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integer mem_cnt;
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initial begin
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initial begin
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Dq_reg = {data_bits{1'bz}};
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Dq_reg = {data_bits{1'bz}};
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Data_in_enable = 0; Data_out_enable = 0;
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Data_in_enable = 0; Data_out_enable = 0;
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Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
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Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
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Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
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Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
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RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
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RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
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RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
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RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
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RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
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RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
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RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
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RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
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$timeformat (-9, 1, " ns", 12);
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$timeformat (-9, 1, " ns", 12);
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//`define INIT_CLEAR_MEM_BANKS
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`ifdef INIT_CLEAR_MEM_BANKS // Added, jb
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// Initialse the memory before we use it, clearing x's
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for(mem_cnt = 0; mem_cnt < mem_sizes; mem_cnt = mem_cnt + 1)
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begin
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Bank0[mem_cnt] = 0;
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Bank1[mem_cnt] = 0;
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Bank2[mem_cnt] = 0;
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Bank3[mem_cnt] = 0;
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end
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`endif
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`ifdef PRELOAD_RAM // Added jb
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$display("* Preloading SDRAM bank 0.\n");
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// Uses the vmem file for the internal SRAM, so words are 32-bits wide
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// and we need to copy them into the 16-bit wide array, which the simulator
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// can't figure out how to do, so we'll do it manually here.
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$readmemh("sram.vmem", Bank0_32bit);
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for (mem_cnt=0;mem_cnt < (mem_sizes/2); mem_cnt = mem_cnt + 1)
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begin
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Bank0[(mem_cnt*2)+1] = Bank0_32bit[mem_cnt][15:0];
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Bank0[(mem_cnt*2)] = Bank0_32bit[mem_cnt][31:16];
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end
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`endif
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end
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end
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// System clock generator
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// System clock generator
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always begin
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always begin
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@ (posedge Clk) begin
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@ (posedge Clk) begin
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$setuphold(posedge Clk, Ba, tAS, tAH);
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$setuphold(posedge Clk, Ba, tAS, tAH);
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$setuphold(posedge Clk, Dqm, tCMS, tCMH);
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$setuphold(posedge Clk, Dqm, tCMS, tCMH);
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$setuphold(posedge Dq_chk, Dq, tDS, tDH);
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$setuphold(posedge Dq_chk, Dq, tDS, tDH);
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endspecify
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endspecify
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task get_byte;
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input [31:0] addr;
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output [7:0] data;
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reg [1:0] bank;
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reg [15:0] short;
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begin
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bank = addr[24:23];
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case(bank)
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2'b00:
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short = Bank0[addr[22:1]];
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2'b01:
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short = Bank1[addr[22:1]];
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2'b10:
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short = Bank2[addr[22:1]];
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2'b11:
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short = Bank3[addr[22:1]];
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endcase // case (bank)
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// Get the byte from the short
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if (!addr[0])
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data = short[15:8];
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else
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data = short[7:0];
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//$display("SDRAM addr 0x%0h, bank %0d, short 0x%0h, byte 0x%0h", addr, bank, short, data);
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end
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endtask // get_byte
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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