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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [mt48lc16m16a2.v] - Diff between revs 6 and 44

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Rev 6 Rev 44
Line 35... Line 35...
* 2.0  SH              04/30/2002  - Second release
* 2.0  SH              04/30/2002  - Second release
*      Micron Technology Inc.
*      Micron Technology Inc.
*
*
**************************************************************************/
**************************************************************************/
 
 
`timescale 1ns / 1ps
`include "timescale.v"
 
 
module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
 
 
    parameter addr_bits =      13;
    parameter addr_bits =      13;
    parameter data_bits =      16;
    parameter data_bits =      16;

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