| Line 132... |
Line 132... |
//
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//
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// Limitation: only a small subset of register file RAMs
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// Limitation: only a small subset of register file RAMs
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// are supported
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// are supported
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//
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//
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task display_arch_state;
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task display_arch_state;
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input exception;
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reg [5:0] i;
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reg [5:0] i;
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reg [31:0] r;
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reg [31:0] r;
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integer j;
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integer j;
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begin
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begin
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`ifdef OR1200_MONITOR_EXEC_STATE
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`ifdef OR1200_MONITOR_EXEC_STATE
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ref = ref + 1;
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ref = ref + 1;
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`ifdef OR1200_MONITOR_LOOKUP
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`ifdef OR1200_MONITOR_LOOKUP
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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`endif
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`endif
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if(exception)
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns,
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`OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
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`OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
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else
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns,
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns,
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`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
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`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
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`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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`ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
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`ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
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if(!exception) begin
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$fwrite(fexe,"\t");
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$fwrite(fexe,"\t");
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// Decode the instruction, print it out
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// Decode the instruction, print it out
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or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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end
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`endif
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`endif
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for(i = 0; i < 32; i = i + 1) begin
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for(i = 0; i < 32; i = i + 1) begin
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if (i % 4 == 0)
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if (i % 4 == 0)
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$fdisplay(fexe);
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$fdisplay(fexe);
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get_gpr(i, r);
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get_gpr(i, r);
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| Line 165... |
Line 174... |
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
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$fwrite(fexe, "EEAR0: %h ", r);
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$fwrite(fexe, "EEAR0: %h ", r);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
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$fdisplay(fexe, "ESR0 : %h", r);
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$fdisplay(fexe, "ESR0 : %h", r);
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`endif // `ifdef OR1200_MONITOR_EXEC_STATE
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`endif // `ifdef OR1200_MONITOR_EXEC_STATE
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`ifdef OR1200_DISPLAY_EXECUTED
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ref = ref + 1;
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`ifdef OR1200_MONITOR_LOOKUP
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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`endif
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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`endif
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insns = insns + 1;
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insns = insns + 1;
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end
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end
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endtask // display_arch_state
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endtask // display_arch_state
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/* Keep a trace buffer of the last lot of instructions and addresses
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/* Keep a trace buffer of the last lot of instructions and addresses
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| Line 231... |
Line 233... |
end
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end
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end
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end
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endtask // monitor_for_crash
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endtask // monitor_for_crash
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//
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// Write state of the OR1200 registers into a file; version for exception
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//
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task display_arch_state_except;
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reg [5:0] i;
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reg [31:0] r;
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integer j;
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begin
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`ifdef OR1200_MONITOR_EXEC_STATE
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ref = ref + 1;
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`ifdef OR1200_MONITOR_LOOKUP
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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`endif
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
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for(i = 0; i < 32; i = i + 1) begin
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if (i % 4 == 0)
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$fdisplay(fexe);
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get_gpr(i, r);
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$fwrite(fexe, "GPR%d: %h ", i, r);
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end
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$fdisplay(fexe);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
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$fwrite(fexe, "SR : %h ", r);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
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$fwrite(fexe, "EPCR0: %h ", r);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
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$fwrite(fexe, "EEAR0: %h ", r);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
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$fdisplay(fexe, "ESR0 : %h", r);
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insns = insns + 1;
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`endif // `ifdef OR1200_MONITOR_EXEC_STATE
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`ifdef OR1200_DISPLAY_EXECUTED
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ref = ref + 1;
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`ifdef OR1200_MONITOR_LOOKUP
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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`endif
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns,
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`OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
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`OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
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insns = insns + 1;
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`endif
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end
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endtask
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integer iwb_progress;
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integer iwb_progress;
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reg [31:0] iwb_progress_addr;
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reg [31:0] iwb_progress_addr;
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//
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//
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// WISHBONE bus checker
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// WISHBONE bus checker
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//
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//
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| Line 381... |
Line 337... |
if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
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if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
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| !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
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| !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
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& !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
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& !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
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`OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
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`OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
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begin
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begin
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display_arch_state;
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display_arch_state(0);
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monitor_for_crash;
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monitor_for_crash;
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end
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end
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else
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else
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if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
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if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
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display_arch_state_except;
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display_arch_state(1);
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// small hack to stop simulation (l.nop 1):
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// small hack to stop simulation (l.nop 1):
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if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
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if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
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get_gpr(3, r3);
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get_gpr(3, r3);
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$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
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$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
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`ifdef OR1200_MONITOR_VERBOSE_NOPS
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`ifdef OR1200_MONITOR_VERBOSE_NOPS
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