| Line 37... |
Line 37... |
`include "test-defines.v"
|
`include "test-defines.v"
|
|
|
//
|
//
|
// Top of OR1200 inside test bench
|
// Top of OR1200 inside test bench
|
//
|
//
|
`define OR1200_TOP orpsoc_testbench.dut.or1200_top
|
`define OR1200_TOP orpsoc_testbench.dut.or1200_top0
|
|
|
//
|
//
|
// Define to enable lookup file generation
|
// Define to enable lookup file generation
|
//
|
//
|
//`define OR1200_MONITOR_LOOKUP
|
//`define OR1200_MONITOR_LOOKUP
|
| Line 437... |
Line 437... |
`endif
|
`endif
|
end
|
end
|
|
|
|
|
`ifdef VERSATILE_SDRAM
|
`ifdef VERSATILE_SDRAM
|
`define SDRAM_TOP design_testbench.sdram0
|
`define SDRAM_TOP orpsoc_testbench.sdram0
|
// Bit selects to define the bank
|
// Bit selects to define the bank
|
// 32 MB part with 4 banks
|
// 32 MB part with 4 banks
|
`define SDRAM_BANK_SEL_BITS 24:23
|
`define SDRAM_BANK_SEL_BITS 24:23
|
`define SDRAM_WORD_SEL_TOP_BIT 22
|
`define SDRAM_WORD_SEL_TOP_BIT 22
|
// Gets instruction word from correct bank
|
// Gets instruction word from correct bank
|
| Line 463... |
Line 463... |
|
|
endtask // get_insn_from_sdram
|
endtask // get_insn_from_sdram
|
`endif // `ifdef VERSATILE_SDRAM
|
`endif // `ifdef VERSATILE_SDRAM
|
|
|
`ifdef XILINX_DDR2
|
`ifdef XILINX_DDR2
|
`define DDR2_TOP design_testbench.gen_cs[0]
|
`define DDR2_TOP orpsoc_testbench.gen_cs[0]
|
// Gets instruction word from correct bank
|
// Gets instruction word from correct bank
|
task get_insn_from_xilinx_ddr2;
|
task get_insn_from_xilinx_ddr2;
|
input [31:0] addr;
|
input [31:0] addr;
|
output [31:0] insn;
|
output [31:0] insn;
|
reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,ddr2_array_line3;
|
reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,ddr2_array_line3;
|
