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Line 35... |
`include "or1200_defines.v"
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`include "or1200_defines.v"
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`include "orpsoc-testbench-defines.v"
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`include "orpsoc-testbench-defines.v"
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`include "test-defines.v"
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`include "test-defines.v"
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//
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//
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// Top of TB
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//
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`define TB_TOP orpsoc_testbench
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//
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// Top of DUT
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//
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`define DUT_TOP `TB_TOP.dut
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//
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// Top of OR1200 inside test bench
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// Top of OR1200 inside test bench
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//
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//
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`define OR1200_TOP orpsoc_testbench.dut.or1200_top0
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`define OR1200_TOP `DUT_TOP.or1200_top0
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//
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//
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// Define to enable lookup file generation
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// Define to enable lookup file generation
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//
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//
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//`define OR1200_MONITOR_LOOKUP
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//`define OR1200_MONITOR_LOOKUP
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Line 80... |
`define OR1200_MONITOR_SPRS
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`define OR1200_MONITOR_SPRS
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`define OR1200_MONITOR_LOOKUP
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`define OR1200_MONITOR_LOOKUP
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`endif
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`endif
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//
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//
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// Memory coherence checking (double check instruction in fetch stage against
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// what is in memory.)
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//
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//`define MEM_COHERENCE_CHECK
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//
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// Top of OR1200 inside test bench
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// Top of OR1200 inside test bench
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//
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//
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`define CPU or1200
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`define CPU or1200
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`define CPU_cpu or1200_cpu
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`define CPU_cpu or1200_cpu
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`define CPU_rf or1200_rf
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`define CPU_rf or1200_rf
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Line 452... |
`OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
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`OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
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`endif
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`endif
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end
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end
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`ifdef RAM_WB
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`define RAM_WB_TOP `DUT_TOP.wb_ram_b3_0
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task get_insn_from_wb_ram;
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input [31:0] addr;
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output [31:0] insn;
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begin
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insn = `RAM_WB_TOP.mem[addr[31:2]];
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end
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endtask // get_insn_from_wb_ram
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`endif
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`ifdef VERSATILE_SDRAM
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`ifdef VERSATILE_SDRAM
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`define SDRAM_TOP orpsoc_testbench.sdram0
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`define SDRAM_TOP `TB_TOP.sdram0
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// Bit selects to define the bank
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// Bit selects to define the bank
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// 32 MB part with 4 banks
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// 32 MB part with 4 banks
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`define SDRAM_BANK_SEL_BITS 24:23
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`define SDRAM_BANK_SEL_BITS 24:23
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`define SDRAM_WORD_SEL_TOP_BIT 22
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`define SDRAM_WORD_SEL_TOP_BIT 22
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// Gets instruction word from correct bank
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// Gets instruction word from correct bank
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Line 490... |
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endtask // get_insn_from_sdram
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endtask // get_insn_from_sdram
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`endif // `ifdef VERSATILE_SDRAM
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`endif // `ifdef VERSATILE_SDRAM
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`ifdef XILINX_DDR2
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`ifdef XILINX_DDR2
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`define DDR2_TOP orpsoc_testbench.gen_cs[0]
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`define DDR2_TOP `TB_TOP.gen_cs[0]
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// Gets instruction word from correct bank
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// Gets instruction word from correct bank
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task get_insn_from_xilinx_ddr2;
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task get_insn_from_xilinx_ddr2;
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input [31:0] addr;
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input [31:0] addr;
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output [31:0] insn;
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output [31:0] insn;
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reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,ddr2_array_line3;
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reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
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ddr2_array_line3;
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integer word_in_line_num;
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integer word_in_line_num;
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begin
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begin
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// Get our 4 128-bit chunks (8 half-words in each!! Confused yet?), 16 words total
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// Get our 4 128-bit chunks (8 half-words in each!! Confused yet?),
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// 16 words total
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`DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
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`DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
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`DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
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`DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
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`DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
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`DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
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`DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
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`DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
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case (addr[5:2])
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case (addr[5:2])
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Line 606... |
`endif
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`endif
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`ifdef XILINX_DDR2
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`ifdef XILINX_DDR2
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4'h0:
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4'h0:
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get_insn_from_xilinx_ddr2(id_pc, insn);
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get_insn_from_xilinx_ddr2(id_pc, insn);
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`endif
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`endif
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`ifdef RAM_WB
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4'h0:
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get_insn_from_wb_ram(id_pc, insn);
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`endif
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4'hf:
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4'hf:
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// Flash isn't stored in a memory, it's an FSM so just skip/ignore
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// Flash isn't stored in a memory, it's an FSM so just skip/ignore
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insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
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insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
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default:
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default:
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begin
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begin
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Line 627... |
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reg [31:0] mem_word;
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reg [31:0] mem_word;
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reg [31:0] last_addr = 0;
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reg [31:0] last_addr = 0;
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reg [31:0] last_mem_word;
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reg [31:0] last_mem_word;
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//`define TRIGGER_FOR_CHECK (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
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`ifdef MEM_COHERENCE_CHECK
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// Disabled:
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`define MEM_COHERENCE_TRIGGER (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
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`define TRIGGER_FOR_CHECK 0
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`define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
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`define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
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`define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
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`define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
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// Check instruction in decode stage is what is in the RAM
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// Check instruction in decode stage is what is in the RAM
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always @(posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
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always @(posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
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begin
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begin
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if (`TRIGGER_FOR_CHECK)
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if (`MEM_COHERENCE_TRIGGER)
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begin
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begin
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// Check if it's a new PC - will also get triggered if the
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// Check if it's a new PC - will also get triggered if the
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// instruction has changed since we last checked it
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// instruction has changed since we last checked it
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if ((`PC_TO_CHECK !== last_addr) ||
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if ((`PC_TO_CHECK !== last_addr) ||
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(last_mem_word != `INSN_TO_CHECK))
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(last_mem_word != `INSN_TO_CHECK))
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Line 662... |
last_mem_word = mem_word;
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last_mem_word = mem_word;
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end // if (`PC_TO_CHECK !== last_addr)
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end // if (`PC_TO_CHECK !== last_addr)
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end
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end
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end // always @ (posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
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end // always @ (posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
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`endif // `ifdef MEM_COHERENCE_CHECK
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/////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////
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// Instruction decode task
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// Instruction decode task
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/////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////
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