OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Diff between revs 449 and 456

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 449 Rev 456
Line 74... Line 74...
// Enable disassembly of instructions in execution state log
// Enable disassembly of instructions in execution state log
//
//
//`define OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
//`define OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
 
 
//
//
 
// Enable verbose report l.nops (to both general log file and stdout)
 
//
 
`define OR1200_MONITOR_VERBOSE_NOPS
 
 
 
//
// Enable monitoring of control and execution flow (experimental)
// Enable monitoring of control and execution flow (experimental)
//
//
//`define OR1200_SYSTEM_CHECKER
//`define OR1200_SYSTEM_CHECKER
 
 
// Can either individually enable things above, or usually have the scripts
// Can either individually enable things above, or usually have the scripts
Line 448... Line 453...
            display_arch_state_except;
            display_arch_state_except;
        // small hack to stop simulation (l.nop 1):
        // small hack to stop simulation (l.nop 1):
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
           get_gpr(3, r3);
           get_gpr(3, r3);
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
 
`ifdef OR1200_MONITOR_VERBOSE_NOPS
 
           $display("%t: l.nop exit (%h)", $time, r3);
 
`endif
           $finish;
           $finish;
        end
        end
        // debug if test (l.nop 10)
        // debug if test (l.nop 10)
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
        end
        end
        // simulation reports (l.nop 2)
        // simulation reports (l.nop 2)
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
           get_gpr(3, r3);
           get_gpr(3, r3);
           $fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
           $fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
 
`ifdef OR1200_MONITOR_VERBOSE_NOPS
 
           $display("%t: l.nop report (%h)", $time, r3);
 
`endif
        end
        end
        // simulation printfs (l.nop 3)
        // simulation printfs (l.nop 3)
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
           get_gpr(3, r3);
           get_gpr(3, r3);
           $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
           $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.