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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Diff between revs 456 and 468

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Rev 456 Rev 468
Line 454... Line 454...
        // small hack to stop simulation (l.nop 1):
        // small hack to stop simulation (l.nop 1):
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
           get_gpr(3, r3);
           get_gpr(3, r3);
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
`ifdef OR1200_MONITOR_VERBOSE_NOPS
`ifdef OR1200_MONITOR_VERBOSE_NOPS
           $display("%t: l.nop exit (%h)", $time, r3);
           $display("exit(%h)",r3);
`endif
`endif
           $finish;
           $finish;
        end
        end
        // debug if test (l.nop 10)
        // debug if test (l.nop 10)
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
        end
        end
        // simulation reports (l.nop 2)
        // simulation reports (l.nop 2)
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
           get_gpr(3, r3);
           get_gpr(3, r3);
           $fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
           $fdisplay(fgeneral, "%t: l.nop report (0x%h)", $time, r3);
`ifdef OR1200_MONITOR_VERBOSE_NOPS
`ifdef OR1200_MONITOR_VERBOSE_NOPS
           $display("%t: l.nop report (%h)", $time, r3);
           $display("report (0x%h);", r3);
`endif
`endif
        end
        end
        // simulation printfs (l.nop 3)
        // simulation printfs (l.nop 3)
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
           get_gpr(3, r3);
           get_gpr(3, r3);
Line 501... Line 501...
 `define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
 `define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
   task get_insn_from_wb_ram;
   task get_insn_from_wb_ram;
      input [31:0] addr;
      input [31:0] addr;
      output [31:0] insn;
      output [31:0] insn;
      begin
      begin
         insn = `RAM_WB_TOP.get_mem(addr);
         insn = `RAM_WB_TOP.get_mem32(addr);
      end
      end
   endtask // get_insn_from_wb_ram
   endtask // get_insn_from_wb_ram
`endif
`endif
 
 
`ifdef VERSATILE_SDRAM
`ifdef VERSATILE_SDRAM

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