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Line 35... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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`include "orpsoc-testbench-defines.v"
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`include "or1200_monitor_defines.v"
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`include "test-defines.v"
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`include "test-defines.v"
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//
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// Top of TB
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//
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`define TB_TOP orpsoc_testbench
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//
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// Top of DUT
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//
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`define DUT_TOP `TB_TOP.dut
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//
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// Top of OR1200 inside test bench
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//
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`define OR1200_TOP `DUT_TOP.or1200_top0
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//
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// Define to enable lookup file generation
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//
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//`define OR1200_MONITOR_LOOKUP
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//
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// Define to enable SPR access log file generation
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//
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//`define OR1200_MONITOR_SPRS
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//
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// Enable logging of state during execution
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//
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//`define OR1200_MONITOR_EXEC_STATE
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//
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// Enable disassembly of instructions in execution state log
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//
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//`define OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
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//
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// Enable verbose report l.nops (to both general log file and stdout)
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//
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`define OR1200_MONITOR_VERBOSE_NOPS
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//
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// Enable monitoring of control and execution flow (experimental)
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//
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//`define OR1200_SYSTEM_CHECKER
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// Can either individually enable things above, or usually have the scripts
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// running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to
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// enable them all.
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`ifdef PROCESSOR_MONITOR_ENABLE_LOGS
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`define OR1200_MONITOR_EXEC_STATE
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`define OR1200_MONITOR_SPRS
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`define OR1200_MONITOR_LOOKUP
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`endif
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//
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// Memory coherence checking (double check instruction in fetch stage against
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// what is in memory.) Useful for cache controller development.
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//
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//`define MEM_COHERENCE_CHECK
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//
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// Top of OR1200 inside test bench
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//
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`define CPU or1200
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`define CPU_cpu or1200_cpu
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`define CPU_rf or1200_rf
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`define CPU_except or1200_except
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`define CPU_ctrl or1200_ctrl
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`define CPU_sprs or1200_sprs
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`define CPU_immu_top or1200_immu_top
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`define CPU_immu_tlb or1200_immu_tlb
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`define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk
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`define OR1K_OPCODE_POS 31:26
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`define OR1K_J_BR_IMM_POS 25:0
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`define OR1K_RD_POS 25:21
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`define OR1K_RA_POS 20:16
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`define OR1K_RB_POS 15:11
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`define OR1K_ALU_OP_POS 3:0
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`define OR1K_SHROT_OP_POS 7:6
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`define OR1K_SHROTI_IMM_POS 5:0
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`define OR1K_SF_OP 25:21
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`define OR1K_XSYNC_OP_POS 25:21
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module or1200_monitor;
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module or1200_monitor;
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integer fexe;
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integer fexe;
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integer finsn;
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integer finsn;
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Line 190... |
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$fdisplay(fgeneral, "PC\t\tINSTR");
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$fdisplay(fgeneral, "PC\t\tINSTR");
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for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
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for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
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$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
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$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
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end
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end
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$display("*");
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$display("* or1200_monitor : OR1200 crash detected (suspected CPU PC corruption)");
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$display("*");
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#100 $finish;
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#100 $finish;
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end
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end
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else
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else
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begin
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begin
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for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
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for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
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