OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Diff between revs 491 and 789

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 491 Rev 789
Line 370... Line 370...
        // small hack to stop simulation (l.nop 1):
        // small hack to stop simulation (l.nop 1):
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
           get_gpr(3, r3);
           get_gpr(3, r3);
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
`ifdef OR1200_MONITOR_VERBOSE_NOPS
`ifdef OR1200_MONITOR_VERBOSE_NOPS
           $display("exit(%h)",r3);
       // Note that the 'expect' scripts in or1ksim's test suite look for strings
 
       // like "exit(1)", therefore something like "exit(  1)" would fail.
 
       $display("exit(%0d)",r3);
`endif
`endif
           $finish;
           $finish;
        end
        end
        // debug if test (l.nop 10)
        // debug if test (l.nop 10)
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
Line 383... Line 385...
        // simulation reports (l.nop 2)
        // simulation reports (l.nop 2)
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
           get_gpr(3, r3);
           get_gpr(3, r3);
           $fdisplay(fgeneral, "%t: l.nop report (0x%h)", $time, r3);
           $fdisplay(fgeneral, "%t: l.nop report (0x%h)", $time, r3);
`ifdef OR1200_MONITOR_VERBOSE_NOPS
`ifdef OR1200_MONITOR_VERBOSE_NOPS
 
           // Note that the 'expect' scripts in or1ksim's test suite look for strings
 
           // like "report(0x7ffffffe);", therefore something like "report (0x7ffffffe);"
 
           // (note the extra space character) would fail.
           $display("report (0x%h);", r3);
           $display("report (0x%h);", r3);
`endif
`endif
        end
        end
        // simulation printfs (l.nop 3)
        // simulation printfs (l.nop 3)
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.