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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Diff between revs 57 and 67

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Rev 57 Rev 67
Line 91... Line 91...
//
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
// Development version of RTL. Libraries are missing.
//
//
//
//
 
 
`include "timescale.v"
`include "timescale.v"
`include "or1200_defines.v"
`include "or1200_defines.v"
`include "orpsoc_testbench_defines.v"
 
 
 
//
//
// Top of OR1200 inside test bench
// Top of OR1200 inside test bench
//
//
 
`ifndef OR1200_TOP
`define OR1200_TOP orpsoc_testbench.dut.i_or1k.i_or1200_top
`define OR1200_TOP orpsoc_testbench.dut.i_or1k.i_or1200_top
 
 `include "orpsoc_testbench_defines.v"
 
`else
 
 `include `TESTBENCH_DEFINES
 
`endif
//
//
// Enable display_arch_state task
// Enable display_arch_state task
//
//
//`define OR1200_DISPLAY_ARCH_STATE
//`define OR1200_DISPLAY_ARCH_STATE
 
 
Line 186... Line 190...
   gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
   gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
end
end
 `else
 `else
  `ifdef OR1200_ARTISAN_SDP
  `ifdef OR1200_ARTISAN_SDP
  `else
  `else
 
    `ifdef OR1200_XILINX_RAMB16
 
     `ifdef legacy_model
 
         for(j = 0; j < 32; j = j + 1) begin
 
            gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[gpr_no*32+j];
 
         end
 
     `else
 
         gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[gpr_no];
 
     `endif
 
    `else
gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
  `endif
  `endif
 `endif
 `endif
`endif
`endif
`endif
`endif
 
`endif
         end
         end
 endtask
 endtask
 
 
   //
   //
   // Write state of the OR1200 registers into a file
   // Write state of the OR1200 registers into a file

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