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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Diff between revs 351 and 360

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Rev 351 Rev 360
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//
//////////////////////////////////////////////////////////////////////
// Or1200 Monitor
////                                                              ////
//
////  or1200_monitor                                              ////
 
////                                                              ////
 
////  OR1200 processor monitor module                             ////
 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
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////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
`include "timescale.v"
`include "timescale.v"
`include "or1200_defines.v"
`include "or1200_defines.v"
 
`include "orpsoc-testbench-defines.v"
 
`include "test-defines.v"
 
 
//
//
// Top of OR1200 inside test bench
// Top of OR1200 inside test bench
//
//
`ifndef OR1200_TOP
`define OR1200_TOP orpsoc_testbench.dut.or1200_top
 `define OR1200_TOP orpsoc_testbench.dut.i_or1k.i_or1200_top
 
 `include "orpsoc_testbench_defines.v"
 
`else
 
 `include `TESTBENCH_DEFINES
 
`endif
 
//
//
// Enable display_arch_state task
// Enable display_arch_state task
//
//
//`define OR1200_DISPLAY_ARCH_STATE
//`define OR1200_DISPLAY_ARCH_STATE
 
 
//
//
// Enable disassembly of instructions in execution log
// Enable disassembly of instructions in execution log
//
//
`define OR1200_MONITOR_PRINT_DISASSEMBLY
//`define OR1200_MONITOR_PRINT_DISASSEMBLY
 
 
 
 
//
//
// Top of OR1200 inside test bench
// Top of OR1200 inside test bench
//
//
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   //
   //
   // Initialization
   // Initialization
   //
   //
   initial begin
   initial begin
      ref = 0;
      ref = 0;
      fexe = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-executed.log"});
      fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
      $timeformat (-9, 2, " ns", 12);
      $timeformat (-9, 2, " ns", 12);
      fspr = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-sprs.log"});
      fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
      fgeneral = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-general.log"});
      fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
      flookup = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-lookup.log"});
      flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
      insns = 0;
      insns = 0;
 
 
   end
   end
 
 
   //
   //

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