| Line 1... |
Line 1... |
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//
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// Or1200 Monitor
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//
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's simulation monitor ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Simulation monitor ////
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//// ////
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//// To Do: ////
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//// - move it to bench ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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| Line 38... |
Line 25... |
//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_monitor.v,v $
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// Revision 1.4 2004/04/05 08:46:06 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.3 2003/04/07 01:32:53 lampret
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// Added get_gpr support for OR1200_RFRAM_GENERIC
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//
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// Revision 1.2 2002/08/12 05:38:11 lampret
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// Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log.
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//
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// Revision 1.1 2002/03/28 19:59:55 lampret
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// Added bench directory
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//
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// Revision 1.9 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.8 2002/01/28 01:25:22 lampret
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// Fixed display of new 'void' nop insns.
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//
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// Revision 1.7 2002/01/19 14:10:39 lampret
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// Fixed OR1200_XILINX_RAM32X1D.
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//
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// Revision 1.6 2002/01/18 07:57:56 lampret
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// Added support for reading XILINX_RAM32X1D register file.
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//
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// Revision 1.5 2002/01/14 06:19:35 lampret
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// Added debug model for testing du. Updated or1200_monitor.
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//
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// Revision 1.4 2002/01/03 08:40:15 lampret
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// Added second clock as RISC main clock. Updated or120_monitor.
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//
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// Revision 1.3 2001/11/23 08:50:35 lampret
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// Typos.
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//
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// Revision 1.2 2001/11/10 04:22:55 lampret
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// Modified monitor tu support exceptions.
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//
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// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
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// First import.
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//
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// Revision 1.1 2001/08/20 18:17:52 damjan
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// Initial revision
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//
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// Revision 1.1 2001/08/13 03:37:07 lampret
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// Added monitor.v and timescale.v
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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//
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//
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| Line 109... |
Line 43... |
//
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//
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// Enable display_arch_state task
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// Enable display_arch_state task
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//
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//
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//`define OR1200_DISPLAY_ARCH_STATE
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//`define OR1200_DISPLAY_ARCH_STATE
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//
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// Top of OR1200 inside test bench
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//
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`define CPU or1200
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`define CPU_cpu or1200_cpu
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`define CPU_rf or1200_rf
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`define CPU_except or1200_except
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`define CPU_ctrl or1200_ctrl
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`define CPU_sprs or1200_sprs
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module or1200_monitor;
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module or1200_monitor;
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integer fexe;
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integer fexe;
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reg [23:0] ref;
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reg [23:0] ref;
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integer fspr;
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integer fspr;
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integer fgeneral;
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integer fgeneral;
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integer flookup;
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integer flookup;
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integer r3;
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integer r3;
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integer insns;
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integer insns;
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//
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//
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// Initialization
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// Initialization
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//
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//
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initial begin
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initial begin
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ref = 0;
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ref = 0;
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| Line 141... |
Line 86... |
task get_gpr;
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task get_gpr;
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input [4:0] gpr_no;
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input [4:0] gpr_no;
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output [31:0] gpr;
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output [31:0] gpr;
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integer j;
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integer j;
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begin
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begin
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`ifdef OR1200_RFRAM_GENERIC
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`ifdef OR1200_RFRAM_GENERIC
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for(j = 0; j < 32; j = j + 1) begin
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for(j = 0; j < 32; j = j + 1) begin
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gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no*32+j];
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gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
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end
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end
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`else
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`else
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`ifdef OR1200_XILINX_RAM32X1D
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//gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
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gpr[0] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[gpr_no];
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gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
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gpr[1] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[gpr_no];
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gpr[2] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[gpr_no];
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gpr[3] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[gpr_no];
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gpr[4] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[gpr_no];
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gpr[5] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[gpr_no];
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gpr[6] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[gpr_no];
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gpr[7] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[gpr_no];
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gpr[8] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[gpr_no];
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gpr[9] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[gpr_no];
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gpr[10] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[gpr_no];
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gpr[11] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[gpr_no];
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gpr[12] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[gpr_no];
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gpr[13] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[gpr_no];
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gpr[14] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[gpr_no];
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gpr[15] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[gpr_no];
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gpr[16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[gpr_no];
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gpr[17] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[gpr_no];
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gpr[18] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[gpr_no];
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gpr[19] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[gpr_no];
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gpr[20] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[gpr_no];
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gpr[21] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[gpr_no];
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gpr[22] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[gpr_no];
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gpr[23] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[gpr_no];
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gpr[24] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[gpr_no];
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gpr[25] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[gpr_no];
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gpr[26] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[gpr_no];
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gpr[27] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[gpr_no];
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gpr[28] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[gpr_no];
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gpr[29] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[gpr_no];
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gpr[30] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[gpr_no];
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gpr[31] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[gpr_no];
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`else
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`ifdef OR1200_XILINX_RAMB4
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for(j = 0; j < 16; j = j + 1) begin
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gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[gpr_no*16+j];
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end
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for(j = 0; j < 16; j = j + 1) begin
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gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
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end
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`else
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`ifdef OR1200_ARTISAN_SDP
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`else
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`ifdef OR1200_XILINX_RAMB16
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`ifdef legacy_model
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for(j = 0; j < 32; j = j + 1) begin
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gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[gpr_no*32+j];
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end
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`else
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gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[gpr_no];
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`endif
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`else
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gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
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`endif
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`endif
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`endif
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`endif
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`endif
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`endif
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end
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end
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endtask
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endtask
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//
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//
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// Write state of the OR1200 registers into a file
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// Write state of the OR1200 registers into a file
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| Line 222... |
Line 116... |
integer j;
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integer j;
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begin
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begin
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`ifdef OR1200_DISPLAY_ARCH_STATE
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`ifdef OR1200_DISPLAY_ARCH_STATE
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ref = ref + 1;
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ref = ref + 1;
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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for(i = 0; i < 32; i = i + 1) begin
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for(i = 0; i < 32; i = i + 1) begin
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if (i % 4 == 0)
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if (i % 4 == 0)
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$fdisplay(fexe);
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$fdisplay(fexe);
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get_gpr(i, r);
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get_gpr(i, r);
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$fwrite(fexe, "GPR%d: %h ", i, r);
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$fwrite(fexe, "GPR%d: %h ", i, r);
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end
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end
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$fdisplay(fexe);
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$fdisplay(fexe);
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
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$fwrite(fexe, "SR : %h ", r);
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$fwrite(fexe, "SR : %h ", r);
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
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$fwrite(fexe, "EPCR0: %h ", r);
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$fwrite(fexe, "EPCR0: %h ", r);
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
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$fwrite(fexe, "EEAR0: %h ", r);
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$fwrite(fexe, "EEAR0: %h ", r);
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
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$fdisplay(fexe, "ESR0 : %h", r);
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$fdisplay(fexe, "ESR0 : %h", r);
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insns = insns + 1;
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`endif // `ifdef OR1200_DISPLAY_ARCH_STATE
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`endif
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`ifdef OR1200_DISPLAY_EXECUTED
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end
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endtask // display_arch_state
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//
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// Write state of the OR1200 registers into a file; version for exception
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//
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task display_arch_state_except;
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reg [5:0] i;
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reg [31:0] r;
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integer j;
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begin
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`ifdef OR1200_DISPLAY_ARCH_STATE
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ref = ref + 1;
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ref = ref + 1;
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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for(i = 0; i < 32; i = i + 1) begin
|
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if (i % 4 == 0)
|
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$fdisplay(fexe);
|
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get_gpr(i, r);
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$fwrite(fexe, "GPR%d: %h ", i, r);
|
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end
|
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$fdisplay(fexe);
|
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
|
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$fwrite(fexe, "SR : %h ", r);
|
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
|
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$fwrite(fexe, "EPCR0: %h ", r);
|
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
|
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$fwrite(fexe, "EEAR0: %h ", r);
|
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
|
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$fdisplay(fexe, "ESR0 : %h", r);
|
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insns = insns + 1;
|
|
`endif
|
`endif
|
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insns = insns + 1;
|
end
|
end
|
endtask // display_arch_state_except
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endtask // display_arch_state
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|
|
/* Keep a trace buffer of the last lot of instructions and addresses
|
/* Keep a trace buffer of the last lot of instructions and addresses
|
* "executed",as read from the writeback stage, and cause a $finish if we hit
|
* "executed",as read from the writeback stage, and cause a $finish if we hit
|
* an instruction that is invalid, such as all zeros.
|
* an instruction that is invalid, such as all zeros.
|
* Currently, only breaks on an all zero instruction, but should probably be
|
* Currently, only breaks on an all zero instruction, but should probably be
|
| Line 288... |
Line 155... |
integer num_nul_inst;
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integer num_nul_inst;
|
initial num_nul_inst = 0;
|
initial num_nul_inst = 0;
|
|
|
task monitor_for_crash;
|
task monitor_for_crash;
|
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
|
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
|
reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of 32 instructions
|
//Trace buffer of 32 instructions
|
reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of the addresses of those instructions
|
reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
|
|
//Trace buffer of the addresses of those instructions
|
|
reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h00000000)
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h00000000)
|
num_nul_inst = num_nul_inst + 1;
|
num_nul_inst = num_nul_inst + 1;
|
|
else
|
|
num_nul_inst = 0; // Reset it
|
|
|
if (num_nul_inst == 1000) // Sat a loop a bit too long...
|
if (num_nul_inst == 1000) // Sat a loop a bit too long...
|
begin
|
begin
|
$fdisplay(fgeneral, "ERROR - no instruction at PC %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc);
|
$fdisplay(fgeneral, "ERROR - no instruction at PC %h",
|
$fdisplay(fgeneral, "Crash trace: Last %d instructions: ",`OR1200_MONITOR_CRASH_TRACE_SIZE);
|
`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
|
|
$fdisplay(fgeneral, "Crash trace: Last %d instructions: ",
|
|
`OR1200_MONITOR_CRASH_TRACE_SIZE);
|
|
|
$fdisplay(fgeneral, "PC\t\tINSTR");
|
$fdisplay(fgeneral, "PC\t\tINSTR");
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
|
$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
|
$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
|
end
|
end
|
| Line 313... |
Line 186... |
begin
|
begin
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
|
insn_trace[i] = insn_trace[i-1];
|
insn_trace[i] = insn_trace[i-1];
|
addr_trace[i] = addr_trace[i-1];
|
addr_trace[i] = addr_trace[i-1];
|
end
|
end
|
insn_trace[0] = `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn;
|
insn_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn;
|
addr_trace[0] = `OR1200_TOP.or1200_cpu.or1200_except.wb_pc;
|
addr_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc;
|
end
|
end
|
|
|
end
|
end
|
endtask // monitor_for_crash
|
endtask // monitor_for_crash
|
|
|
|
|
|
//
|
|
// Write state of the OR1200 registers into a file; version for exception
|
|
//
|
|
task display_arch_state_except;
|
|
reg [5:0] i;
|
|
reg [31:0] r;
|
|
integer j;
|
|
begin
|
|
`ifdef OR1200_DISPLAY_ARCH_STATE
|
|
ref = ref + 1;
|
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
|
|
for(i = 0; i < 32; i = i + 1) begin
|
|
if (i % 4 == 0)
|
|
$fdisplay(fexe);
|
|
get_gpr(i, r);
|
|
$fwrite(fexe, "GPR%d: %h ", i, r);
|
|
end
|
|
$fdisplay(fexe);
|
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
|
|
$fwrite(fexe, "SR : %h ", r);
|
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
|
|
$fwrite(fexe, "EPCR0: %h ", r);
|
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
|
|
$fwrite(fexe, "EEAR0: %h ", r);
|
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
|
|
$fdisplay(fexe, "ESR0 : %h", r);
|
|
insns = insns + 1;
|
|
`endif // `ifdef OR1200_DISPLAY_ARCH_STATE
|
|
`ifdef OR1200_DISPLAY_EXECUTED
|
|
ref = ref + 1;
|
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns,
|
|
`OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
|
|
`OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
|
|
insns = insns + 1;
|
|
`endif
|
|
|
|
end
|
|
endtask
|
|
|
integer iwb_progress;
|
integer iwb_progress;
|
reg [31:0] iwb_progress_addr;
|
reg [31:0] iwb_progress_addr;
|
//
|
//
|
// WISHBONE bus checker
|
// WISHBONE bus checker
|
//
|
//
|
| Line 363... |
Line 278... |
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
|
if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
|
/* #100 $finish;*/
|
#100 $finish;
|
end
|
end
|
end
|
end
|
|
|
integer dwb_progress;
|
integer dwb_progress;
|
reg [31:0] dwb_progress_addr;
|
reg [31:0] dwb_progress_addr;
|
| Line 416... |
Line 331... |
// Hooks for:
|
// Hooks for:
|
// - displaying registers
|
// - displaying registers
|
// - end of simulation
|
// - end of simulation
|
// - access to SPRs
|
// - access to SPRs
|
//
|
//
|
always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
|
always @(posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
|
if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
|
#2;
|
// #2;
|
if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
|
if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
|
&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
|
| !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
|
|
& !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
|
|
`OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
|
begin
|
begin
|
display_arch_state;
|
display_arch_state;
|
monitor_for_crash;
|
monitor_for_crash;
|
end
|
end
|
else
|
else
|
if (`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe)
|
if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
|
display_arch_state_except;
|
display_arch_state_except;
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
|
// small hack to stop simulation (l.nop 1):
|
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
|
get_gpr(3, r3);
|
get_gpr(3, r3);
|
$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
|
$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
|
$finish;
|
$finish;
|
end
|
end
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_000a) begin // debug if test (l.nop 10)
|
// debug if test (l.nop 10)
|
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
|
$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
|
$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
|
`ifdef DBG_IF_MODEL
|
`ifdef DBG_IF_MODEL
|
xess_top.i_xess_fpga.dbg_if_model.dbg_if_test_go = 1;
|
xess_top.i_xess_fpga.dbg_if_model.dbg_if_test_go = 1;
|
`endif
|
`endif
|
end
|
end
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
|
// simulation reports (l.nop 2)
|
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
|
get_gpr(3, r3);
|
get_gpr(3, r3);
|
$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
|
$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
|
end
|
end
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
|
// simulation printfs (l.nop 3)
|
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
|
get_gpr(3, r3);
|
get_gpr(3, r3);
|
$fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
|
$fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
|
end
|
end
|
if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR) // l.mtspr
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
|
|
// simulation putc (l.nop 4)
|
|
get_gpr(3, r3);
|
|
$write("%c", r3);
|
|
$fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
|
|
end
|
|
if (`OR1200_TOP.`CPU_cpu.alu_op/*`CPU_sprs.sprs_op*/ ==
|
|
`OR1200_ALUOP_MTSR) // l.mtspr
|
$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
|
$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
|
`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dat_o);
|
`OR1200_TOP.`CPU_cpu.alu_op/*`CPU_sprs.spr_addr*/,
|
if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR) // l.mfspr
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
|
|
if (`OR1200_TOP.`CPU_cpu.alu_op/*`CPU_sprs.sprs_op*/ ==
|
|
`OR1200_ALUOP_MFSR) // l.mfspr
|
$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
|
$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
|
`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
|
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
|
|
end
|
|
|
|
|
|
`ifdef VERSATILE_SDRAM
|
|
`define SDRAM_TOP design_testbench.sdram0
|
|
// Bit selects to define the bank
|
|
// 32 MB part with 4 banks
|
|
`define SDRAM_BANK_SEL_BITS 24:23
|
|
`define SDRAM_WORD_SEL_TOP_BIT 22
|
|
// Gets instruction word from correct bank
|
|
task get_insn_from_sdram;
|
|
input [31:0] addr;
|
|
output [31:0] insn;
|
|
reg [`SDRAM_WORD_SEL_TOP_BIT-1:0] word_addr;
|
|
|
|
begin
|
|
word_addr = addr[`SDRAM_WORD_SEL_TOP_BIT:2];
|
|
if (addr[`SDRAM_BANK_SEL_BITS] == 2'b00)
|
|
begin
|
|
|
|
//$display("%t: get_insn_from_sdram bank0, word 0x%h, (%h and %h in SDRAM)", $time, word_addr, `SDRAM_TOP.Bank0[{word_addr,1'b0}], `SDRAM_TOP.Bank0[{word_addr,1'b1}]);
|
|
insn[15:0] = `SDRAM_TOP.Bank0[{word_addr,1'b1}];
|
|
insn[31:16] = `SDRAM_TOP.Bank0[{word_addr,1'b0}];
|
|
end
|
|
end
|
|
|
|
endtask // get_insn_from_sdram
|
|
`endif // `ifdef VERSATILE_SDRAM
|
|
|
|
`ifdef XILINX_DDR2
|
|
`define DDR2_TOP design_testbench.gen_cs[0]
|
|
// Gets instruction word from correct bank
|
|
task get_insn_from_xilinx_ddr2;
|
|
input [31:0] addr;
|
|
output [31:0] insn;
|
|
reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,ddr2_array_line3;
|
|
integer word_in_line_num;
|
|
begin
|
|
// Get our 4 128-bit chunks (8 half-words in each!! Confused yet?), 16 words total
|
|
`DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
|
|
`DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
|
|
`DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
|
|
`DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
|
|
case (addr[5:2])
|
|
4'h0:
|
|
begin
|
|
insn[15:0] = ddr2_array_line0[15:0];
|
|
insn[31:16] = ddr2_array_line1[15:0];
|
|
end
|
|
4'h1:
|
|
begin
|
|
insn[15:0] = ddr2_array_line2[15:0];
|
|
insn[31:16] = ddr2_array_line3[15:0];
|
|
end
|
|
4'h2:
|
|
begin
|
|
insn[15:0] = ddr2_array_line0[31:16];
|
|
insn[31:16] = ddr2_array_line1[31:16];
|
|
end
|
|
4'h3:
|
|
begin
|
|
insn[15:0] = ddr2_array_line2[31:16];
|
|
insn[31:16] = ddr2_array_line3[31:16];
|
|
end
|
|
4'h4:
|
|
begin
|
|
insn[15:0] = ddr2_array_line0[47:32];
|
|
insn[31:16] = ddr2_array_line1[47:32];
|
|
end
|
|
4'h5:
|
|
begin
|
|
insn[15:0] = ddr2_array_line2[47:32];
|
|
insn[31:16] = ddr2_array_line3[47:32];
|
|
end
|
|
4'h6:
|
|
begin
|
|
insn[15:0] = ddr2_array_line0[63:48];
|
|
insn[31:16] = ddr2_array_line1[63:48];
|
|
end
|
|
4'h7:
|
|
begin
|
|
insn[15:0] = ddr2_array_line2[63:48];
|
|
insn[31:16] = ddr2_array_line3[63:48];
|
|
end
|
|
4'h8:
|
|
begin
|
|
insn[15:0] = ddr2_array_line0[79:64];
|
|
insn[31:16] = ddr2_array_line1[79:64];
|
|
end
|
|
4'h9:
|
|
begin
|
|
insn[15:0] = ddr2_array_line2[79:64];
|
|
insn[31:16] = ddr2_array_line3[79:64];
|
|
end
|
|
4'ha:
|
|
begin
|
|
insn[15:0] = ddr2_array_line0[95:80];
|
|
insn[31:16] = ddr2_array_line1[95:80];
|
|
end
|
|
4'hb:
|
|
begin
|
|
insn[15:0] = ddr2_array_line2[95:80];
|
|
insn[31:16] = ddr2_array_line3[95:80];
|
|
end
|
|
4'hc:
|
|
begin
|
|
insn[15:0] = ddr2_array_line0[111:96];
|
|
insn[31:16] = ddr2_array_line1[111:96];
|
|
end
|
|
4'hd:
|
|
begin
|
|
insn[15:0] = ddr2_array_line2[111:96];
|
|
insn[31:16] = ddr2_array_line3[111:96];
|
|
end
|
|
4'he:
|
|
begin
|
|
insn[15:0] = ddr2_array_line0[127:112];
|
|
insn[31:16] = ddr2_array_line1[127:112];
|
|
end
|
|
4'hf:
|
|
begin
|
|
insn[15:0] = ddr2_array_line2[127:112];
|
|
insn[31:16] = ddr2_array_line3[127:112];
|
|
end
|
|
endcase // case (addr[5:2])
|
|
end
|
|
endtask // get_insn_from_xilinx_ddr2
|
|
`endif
|
|
|
|
|
|
task get_insn_from_memory;
|
|
input [31:0] id_pc;
|
|
output [31:0] insn;
|
|
begin
|
|
// do a decode of which server we should look in
|
|
case (id_pc[31:28])
|
|
`ifdef VERSATILE_SDRAM
|
|
4'h0:
|
|
get_insn_from_sdram(id_pc, insn);
|
|
`endif
|
|
`ifdef XILINX_DDR2
|
|
4'h0:
|
|
get_insn_from_xilinx_ddr2(id_pc, insn);
|
|
`endif
|
|
4'hf:
|
|
// Flash isn't stored in a memory, it's an FSM so just skip/ignore
|
|
insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
|
|
default:
|
|
begin
|
|
$fdisplay(fgeneral, "%t: Unknown memory server for address 0x%h", $time,id_pc);
|
|
insn = 32'hxxxxxxxx; // Unknown server
|
|
end
|
|
endcase // case (id_pc[31:28])
|
end
|
end
|
|
endtask // get_insn_from_memory
|
|
|
|
|
|
reg [31:0] mem_word;
|
|
reg [31:0] last_addr = 0;
|
|
reg [31:0] last_mem_word;
|
|
|
|
//`define TRIGGER_FOR_CHECK (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
|
|
// Disabled:
|
|
`define TRIGGER_FOR_CHECK 0
|
|
`define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
|
|
`define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
|
|
|
|
// Check instruction in decode stage is what is in the RAM
|
|
always @(posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
|
begin
|
|
if (`TRIGGER_FOR_CHECK)
|
|
begin
|
|
// Check if it's a new PC - will also get triggered if the
|
|
// instruction has changed since we last checked it
|
|
if ((`PC_TO_CHECK !== last_addr) ||
|
|
(last_mem_word != `INSN_TO_CHECK))
|
|
begin
|
|
// Decode stage not void, check instruction
|
|
// get PC
|
|
get_insn_from_memory(`PC_TO_CHECK, mem_word);
|
|
|
|
// Debugging output to prove it's doing something!
|
|
//$display("%t: Checking instruction for address 0x%h - memory had 0x%h, CPU had 0x%h", $time, `PC_TO_CHECK, mem_word, `INSN_TO_CHECK);
|
|
|
|
if (mem_word !== `INSN_TO_CHECK)
|
|
begin
|
|
$fdisplay(fgeneral, "%t: Instruction mismatch for address 0x%h - memory had 0x%h, CPU had 0x%h", $time, `PC_TO_CHECK, mem_word, `INSN_TO_CHECK);
|
|
#20
|
|
$finish;
|
|
end
|
|
last_addr = `PC_TO_CHECK;
|
|
last_mem_word = mem_word;
|
|
end // if (`PC_TO_CHECK !== last_addr)
|
|
end
|
|
end // always @ (posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
