| Line 39... |
Line 39... |
//
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//
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// Top of OR1200 inside test bench
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// Top of OR1200 inside test bench
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//
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//
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`define OR1200_TOP orpsoc_testbench.dut.or1200_top
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`define OR1200_TOP orpsoc_testbench.dut.or1200_top
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//
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// Define to enable lookup file generation
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//
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//`define OR1200_MONITOR_LOOKUP
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//
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// Define to enable SPR access log file generation
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//
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//`define OR1200_MONITOR_SPRS
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//
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//
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// Enable display_arch_state task
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// Enable logging of state during execution
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//
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//
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//`define OR1200_DISPLAY_ARCH_STATE
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//`define OR1200_MONITOR_EXEC_STATE
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//
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//
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// Enable disassembly of instructions in execution log
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// Enable disassembly of instructions in execution state log
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//
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//
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//`define OR1200_MONITOR_PRINT_DISASSEMBLY
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//`define OR1200_MONITOR_PRINT_DISASSEMBLY
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// Can either individually enable things above, or usually have the scripts
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// running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to
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// enable them all.
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`ifdef PROCESSOR_MONITOR_ENABLE_LOGS
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`define OR1200_MONITOR_EXEC_STATE
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`define OR1200_MONITOR_SPRS
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`define OR1200_MONITOR_LOOKUP
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`endif
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//
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//
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// Top of OR1200 inside test bench
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// Top of OR1200 inside test bench
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//
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//
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`define CPU or1200
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`define CPU or1200
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| Line 65... |
Line 83... |
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module or1200_monitor;
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module or1200_monitor;
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integer fexe;
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integer fexe;
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reg [23:0] ref;
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reg [23:0] ref;
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`ifdef OR1200_MONITOR_SPRS
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integer fspr;
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integer fspr;
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`endif
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integer fgeneral;
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integer fgeneral;
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`ifdef OR1200_MONITOR_LOOKUP
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integer flookup;
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integer flookup;
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`endif
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integer r3;
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integer r3;
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integer insns;
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integer insns;
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//
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//
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// Initialization
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// Initialization
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//
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//
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initial begin
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initial begin
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ref = 0;
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ref = 0;
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`ifdef OR1200_MONITOR_EXEC_STATE
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fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
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fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
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`endif
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$timeformat (-9, 2, " ns", 12);
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$timeformat (-9, 2, " ns", 12);
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`ifdef OR1200_MONITOR_SPRS
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fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
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fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
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`endif
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fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
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fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
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`ifdef OR1200_MONITOR_LOOKUP
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flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
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flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
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`endif
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insns = 0;
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insns = 0;
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end
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end
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//
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//
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| Line 121... |
Line 149... |
task display_arch_state;
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task display_arch_state;
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reg [5:0] i;
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reg [5:0] i;
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reg [31:0] r;
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reg [31:0] r;
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integer j;
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integer j;
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begin
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begin
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`ifdef OR1200_DISPLAY_ARCH_STATE
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`ifdef OR1200_MONITOR_EXEC_STATE
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ref = ref + 1;
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ref = ref + 1;
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`ifdef OR1200_MONITOR_LOOKUP
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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`endif
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns,
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns,
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`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
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`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
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`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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`ifdef OR1200_MONITOR_PRINT_DISASSEMBLY
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`ifdef OR1200_MONITOR_PRINT_DISASSEMBLY
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$fwrite(fexe,"\t");
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$fwrite(fexe,"\t");
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| Line 147... |
Line 177... |
$fwrite(fexe, "EPCR0: %h ", r);
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$fwrite(fexe, "EPCR0: %h ", r);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
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$fwrite(fexe, "EEAR0: %h ", r);
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$fwrite(fexe, "EEAR0: %h ", r);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
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$fdisplay(fexe, "ESR0 : %h", r);
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$fdisplay(fexe, "ESR0 : %h", r);
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`endif // `ifdef OR1200_DISPLAY_ARCH_STATE
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`endif // `ifdef OR1200_MONITOR_EXEC_STATE
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`ifdef OR1200_DISPLAY_EXECUTED
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`ifdef OR1200_DISPLAY_EXECUTED
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ref = ref + 1;
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ref = ref + 1;
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`ifdef OR1200_MONITOR_LOOKUP
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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`endif
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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`endif
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`endif
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insns = insns + 1;
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insns = insns + 1;
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end
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end
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endtask // display_arch_state
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endtask // display_arch_state
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| Line 217... |
Line 249... |
task display_arch_state_except;
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task display_arch_state_except;
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reg [5:0] i;
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reg [5:0] i;
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reg [31:0] r;
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reg [31:0] r;
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integer j;
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integer j;
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begin
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begin
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`ifdef OR1200_DISPLAY_ARCH_STATE
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`ifdef OR1200_MONITOR_EXEC_STATE
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ref = ref + 1;
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ref = ref + 1;
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`ifdef OR1200_MONITOR_LOOKUP
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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`endif
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
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for(i = 0; i < 32; i = i + 1) begin
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for(i = 0; i < 32; i = i + 1) begin
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if (i % 4 == 0)
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if (i % 4 == 0)
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$fdisplay(fexe);
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$fdisplay(fexe);
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get_gpr(i, r);
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get_gpr(i, r);
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| Line 237... |
Line 271... |
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
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$fwrite(fexe, "EEAR0: %h ", r);
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$fwrite(fexe, "EEAR0: %h ", r);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
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$fdisplay(fexe, "ESR0 : %h", r);
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$fdisplay(fexe, "ESR0 : %h", r);
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insns = insns + 1;
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insns = insns + 1;
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`endif // `ifdef OR1200_DISPLAY_ARCH_STATE
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`endif // `ifdef OR1200_MONITOR_EXEC_STATE
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`ifdef OR1200_DISPLAY_EXECUTED
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`ifdef OR1200_DISPLAY_EXECUTED
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ref = ref + 1;
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ref = ref + 1;
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`ifdef OR1200_MONITOR_LOOKUP
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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`endif
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns,
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns,
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`OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
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`OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
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`OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
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`OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
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insns = insns + 1;
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insns = insns + 1;
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`endif
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`endif
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| Line 369... |
Line 405... |
$finish;
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$finish;
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end
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end
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// debug if test (l.nop 10)
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// debug if test (l.nop 10)
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if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
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if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
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$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
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$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
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`ifdef DBG_IF_MODEL
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xess_top.i_xess_fpga.dbg_if_model.dbg_if_test_go = 1;
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`endif
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end
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end
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// simulation reports (l.nop 2)
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// simulation reports (l.nop 2)
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if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
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if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
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get_gpr(3, r3);
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get_gpr(3, r3);
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$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
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$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
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| Line 389... |
Line 422... |
// simulation putc (l.nop 4)
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// simulation putc (l.nop 4)
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get_gpr(3, r3);
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get_gpr(3, r3);
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$write("%c", r3);
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$write("%c", r3);
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$fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
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$fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
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end
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end
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if (`OR1200_TOP.`CPU_cpu.alu_op/*`CPU_sprs.sprs_op*/ ==
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`ifdef OR1200_MONITOR_SPRS
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`OR1200_ALUOP_MTSR) // l.mtspr
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if (`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
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$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
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$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
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`OR1200_TOP.`CPU_cpu.alu_op/*`CPU_sprs.spr_addr*/,
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`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
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`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
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`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
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if (`OR1200_TOP.`CPU_cpu.alu_op/*`CPU_sprs.sprs_op*/ ==
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if ((|`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_cs) &
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`OR1200_ALUOP_MFSR) // l.mfspr
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!`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
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$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
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$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
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`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
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`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
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`OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
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`OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
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`endif
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end
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end
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`ifdef VERSATILE_SDRAM
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`ifdef VERSATILE_SDRAM
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`define SDRAM_TOP design_testbench.sdram0
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`define SDRAM_TOP design_testbench.sdram0
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