Line 35... |
Line 35... |
`include "or1200_defines.v"
|
`include "or1200_defines.v"
|
`include "orpsoc-testbench-defines.v"
|
`include "orpsoc-testbench-defines.v"
|
`include "test-defines.v"
|
`include "test-defines.v"
|
|
|
//
|
//
|
|
// Top of TB
|
|
//
|
|
`define TB_TOP orpsoc_testbench
|
|
|
|
//
|
|
// Top of DUT
|
|
//
|
|
`define DUT_TOP `TB_TOP.dut
|
|
|
|
//
|
// Top of OR1200 inside test bench
|
// Top of OR1200 inside test bench
|
//
|
//
|
`define OR1200_TOP orpsoc_testbench.dut.or1200_top0
|
`define OR1200_TOP `DUT_TOP.or1200_top0
|
|
|
//
|
//
|
// Define to enable lookup file generation
|
// Define to enable lookup file generation
|
//
|
//
|
//`define OR1200_MONITOR_LOOKUP
|
//`define OR1200_MONITOR_LOOKUP
|
Line 70... |
Line 80... |
`define OR1200_MONITOR_SPRS
|
`define OR1200_MONITOR_SPRS
|
`define OR1200_MONITOR_LOOKUP
|
`define OR1200_MONITOR_LOOKUP
|
`endif
|
`endif
|
|
|
//
|
//
|
|
// Memory coherence checking (double check instruction in fetch stage against
|
|
// what is in memory.)
|
|
//
|
|
//`define MEM_COHERENCE_CHECK
|
|
|
|
//
|
// Top of OR1200 inside test bench
|
// Top of OR1200 inside test bench
|
//
|
//
|
`define CPU or1200
|
`define CPU or1200
|
`define CPU_cpu or1200_cpu
|
`define CPU_cpu or1200_cpu
|
`define CPU_rf or1200_rf
|
`define CPU_rf or1200_rf
|
Line 436... |
Line 452... |
`OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
|
`endif
|
`endif
|
end
|
end
|
|
|
|
|
|
`ifdef RAM_WB
|
|
`define RAM_WB_TOP `DUT_TOP.wb_ram_b3_0
|
|
task get_insn_from_wb_ram;
|
|
input [31:0] addr;
|
|
output [31:0] insn;
|
|
begin
|
|
insn = `RAM_WB_TOP.mem[addr[31:2]];
|
|
end
|
|
endtask // get_insn_from_wb_ram
|
|
`endif
|
|
|
`ifdef VERSATILE_SDRAM
|
`ifdef VERSATILE_SDRAM
|
`define SDRAM_TOP orpsoc_testbench.sdram0
|
`define SDRAM_TOP `TB_TOP.sdram0
|
// Bit selects to define the bank
|
// Bit selects to define the bank
|
// 32 MB part with 4 banks
|
// 32 MB part with 4 banks
|
`define SDRAM_BANK_SEL_BITS 24:23
|
`define SDRAM_BANK_SEL_BITS 24:23
|
`define SDRAM_WORD_SEL_TOP_BIT 22
|
`define SDRAM_WORD_SEL_TOP_BIT 22
|
// Gets instruction word from correct bank
|
// Gets instruction word from correct bank
|
Line 463... |
Line 490... |
|
|
endtask // get_insn_from_sdram
|
endtask // get_insn_from_sdram
|
`endif // `ifdef VERSATILE_SDRAM
|
`endif // `ifdef VERSATILE_SDRAM
|
|
|
`ifdef XILINX_DDR2
|
`ifdef XILINX_DDR2
|
`define DDR2_TOP orpsoc_testbench.gen_cs[0]
|
`define DDR2_TOP `TB_TOP.gen_cs[0]
|
// Gets instruction word from correct bank
|
// Gets instruction word from correct bank
|
task get_insn_from_xilinx_ddr2;
|
task get_insn_from_xilinx_ddr2;
|
input [31:0] addr;
|
input [31:0] addr;
|
output [31:0] insn;
|
output [31:0] insn;
|
reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,ddr2_array_line3;
|
reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
|
|
ddr2_array_line3;
|
integer word_in_line_num;
|
integer word_in_line_num;
|
begin
|
begin
|
// Get our 4 128-bit chunks (8 half-words in each!! Confused yet?), 16 words total
|
// Get our 4 128-bit chunks (8 half-words in each!! Confused yet?),
|
|
// 16 words total
|
`DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
|
`DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
|
`DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
|
`DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
|
`DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
|
`DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
|
`DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
|
`DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
|
case (addr[5:2])
|
case (addr[5:2])
|
Line 577... |
Line 606... |
`endif
|
`endif
|
`ifdef XILINX_DDR2
|
`ifdef XILINX_DDR2
|
4'h0:
|
4'h0:
|
get_insn_from_xilinx_ddr2(id_pc, insn);
|
get_insn_from_xilinx_ddr2(id_pc, insn);
|
`endif
|
`endif
|
|
`ifdef RAM_WB
|
|
4'h0:
|
|
get_insn_from_wb_ram(id_pc, insn);
|
|
`endif
|
4'hf:
|
4'hf:
|
// Flash isn't stored in a memory, it's an FSM so just skip/ignore
|
// Flash isn't stored in a memory, it's an FSM so just skip/ignore
|
insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
|
insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
|
default:
|
default:
|
begin
|
begin
|
Line 594... |
Line 627... |
|
|
reg [31:0] mem_word;
|
reg [31:0] mem_word;
|
reg [31:0] last_addr = 0;
|
reg [31:0] last_addr = 0;
|
reg [31:0] last_mem_word;
|
reg [31:0] last_mem_word;
|
|
|
//`define TRIGGER_FOR_CHECK (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
|
`ifdef MEM_COHERENCE_CHECK
|
// Disabled:
|
`define MEM_COHERENCE_TRIGGER (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
|
`define TRIGGER_FOR_CHECK 0
|
|
`define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
|
`define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
|
`define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
|
`define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
|
|
|
// Check instruction in decode stage is what is in the RAM
|
// Check instruction in decode stage is what is in the RAM
|
always @(posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
always @(posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
begin
|
begin
|
if (`TRIGGER_FOR_CHECK)
|
if (`MEM_COHERENCE_TRIGGER)
|
begin
|
begin
|
// Check if it's a new PC - will also get triggered if the
|
// Check if it's a new PC - will also get triggered if the
|
// instruction has changed since we last checked it
|
// instruction has changed since we last checked it
|
if ((`PC_TO_CHECK !== last_addr) ||
|
if ((`PC_TO_CHECK !== last_addr) ||
|
(last_mem_word != `INSN_TO_CHECK))
|
(last_mem_word != `INSN_TO_CHECK))
|
Line 629... |
Line 662... |
last_mem_word = mem_word;
|
last_mem_word = mem_word;
|
end // if (`PC_TO_CHECK !== last_addr)
|
end // if (`PC_TO_CHECK !== last_addr)
|
end
|
end
|
end // always @ (posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
end // always @ (posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
|
|
|
`endif // `ifdef MEM_COHERENCE_CHECK
|
|
|
|
|
/////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////
|
// Instruction decode task
|
// Instruction decode task
|
/////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////
|