| Line 229... |
Line 229... |
insns = insns + 1;
|
insns = insns + 1;
|
`endif
|
`endif
|
end
|
end
|
endtask // display_arch_state
|
endtask // display_arch_state
|
|
|
|
//
|
|
// Write state of the OR1200 registers into a file; version for exception
|
|
//
|
|
task display_arch_state_except;
|
|
reg [5:0] i;
|
|
reg [31:0] r;
|
|
integer j;
|
|
begin
|
|
`ifdef OR1200_DISPLAY_ARCH_STATE
|
|
ref = ref + 1;
|
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
|
|
for(i = 0; i < 32; i = i + 1) begin
|
|
if (i % 4 == 0)
|
|
$fdisplay(fexe);
|
|
get_gpr(i, r);
|
|
$fwrite(fexe, "GPR%d: %h ", i, r);
|
|
end
|
|
$fdisplay(fexe);
|
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
|
|
$fwrite(fexe, "SR : %h ", r);
|
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
|
|
$fwrite(fexe, "EPCR0: %h ", r);
|
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
|
|
$fwrite(fexe, "EEAR0: %h ", r);
|
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
|
|
$fdisplay(fexe, "ESR0 : %h", r);
|
|
insns = insns + 1;
|
|
`endif
|
|
end
|
|
endtask // display_arch_state_except
|
|
|
/* Keep a trace buffer of the last lot of instructions and addresses
|
/* Keep a trace buffer of the last lot of instructions and addresses
|
* "executed",as read from the writeback stage, and cause a $finish if we hit
|
* "executed",as read from the writeback stage, and cause a $finish if we hit
|
* an instruction that is invalid, such as all zeros.
|
* an instruction that is invalid, such as all zeros.
|
* Currently, only breaks on an all zero instruction, but should probably be
|
* Currently, only breaks on an all zero instruction, but should probably be
|
* made to break for anything with an X in it too. And of course ideally this
|
* made to break for anything with an X in it too. And of course ideally this
|
| Line 274... |
Line 306... |
end
|
end
|
|
|
end
|
end
|
endtask // monitor_for_crash
|
endtask // monitor_for_crash
|
|
|
|
|
//
|
|
// Write state of the OR1200 registers into a file; version for exception
|
|
//
|
|
task display_arch_state_except;
|
|
reg [5:0] i;
|
|
reg [31:0] r;
|
|
integer j;
|
|
begin
|
|
`ifdef OR1200_DISPLAY_ARCH_STATE
|
|
ref = ref + 1;
|
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
|
|
for(i = 0; i < 32; i = i + 1) begin
|
|
if (i % 4 == 0)
|
|
$fdisplay(fexe);
|
|
get_gpr(i, r);
|
|
$fwrite(fexe, "GPR%d: %h ", i, r);
|
|
end
|
|
$fdisplay(fexe);
|
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
|
|
$fwrite(fexe, "SR : %h ", r);
|
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
|
|
$fwrite(fexe, "EPCR0: %h ", r);
|
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
|
|
$fwrite(fexe, "EEAR0: %h ", r);
|
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
|
|
$fdisplay(fexe, "ESR0 : %h", r);
|
|
insns = insns + 1;
|
|
`endif
|
|
end
|
|
endtask
|
|
|
|
integer iwb_progress;
|
integer iwb_progress;
|
reg [31:0] iwb_progress_addr;
|
reg [31:0] iwb_progress_addr;
|
//
|
//
|
// WISHBONE bus checker
|
// WISHBONE bus checker
|
//
|
//
|
