OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 6 and 40

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 6 Rev 40
Line 122... Line 122...
   assign rst_i = rst;
   assign rst_i = rst;
 
 
   // Tie off some inputs   
   // Tie off some inputs   
   assign spi1_miso_i = 0;
   assign spi1_miso_i = 0;
   assign uart0_srx_i = 1;
   assign uart0_srx_i = 1;
   assign dbg_tdi_i = 1;
 
   assign dbg_tck_i = 0;
 
   assign dbg_tms_i = 1;
 
 
 
 
 
   orpsoc_top dut
   orpsoc_top dut
     (
     (
      // Outputs
      // Outputs
Line 177... Line 174...
      .spi_flash_miso_pad_i             (spi_flash_miso_i),
      .spi_flash_miso_pad_i             (spi_flash_miso_i),
`endif
`endif
      .rst_pad_i                                (rst_i),
      .rst_pad_i                                (rst_i),
      .clk_pad_i                                (clk_i));
      .clk_pad_i                                (clk_i));
 
 
 
`ifdef VPI_DEBUG_ENABLE
 
   // Debugging interface
 
   vpi_debug_module vpi_dbg(
 
                            .tms(dbg_tms_i),
 
                            .tck(dbg_tck_i),
 
                            .tdi(dbg_tdi_i),
 
                            .tdo(dbg_tdo_o));
 
`else
 
   // If no VPI debugging, tie off JTAG inputs
 
   assign dbg_tdi_i = 1;
 
   assign dbg_tck_i = 0;
 
   assign dbg_tms_i = 1;
 
`endif
 
 
 
 
 
 
   // External memories, if enabled
   // External memories, if enabled
`ifdef USE_SDRAM
`ifdef USE_SDRAM
   // SPI Flash
   // SPI Flash
   AT26DFxxx spi_flash
   AT26DFxxx spi_flash
     (
     (

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.