| Line 147... |
Line 147... |
.dbg_tck_pad_i (dbg_tck_i),
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.dbg_tck_pad_i (dbg_tck_i),
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.dbg_tms_pad_i (dbg_tms_i),
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.dbg_tms_pad_i (dbg_tms_i),
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`ifdef USE_ETHERNET
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`ifdef USE_ETHERNET
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// Ethernet ports
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// Ethernet ports
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.eth_md_pad_io (eth_md_io[1:1]),
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.eth_md_pad_io (eth_md_io[1:1]),
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.eth_mdc_pad_o (eth_mdc_o[1:1]),
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.eth_sync_pad_o (eth_sync_o[1:1]),
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.eth_sync_pad_o (eth_sync_o[1:1]),
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.eth_tx_pad_o (eth_tx_o[1:1]),
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.eth_tx_pad_o (eth_tx_o[1:1]),
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.eth_mdc_pad_o (eth_mdc_o[1:1]),
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.eth_rx_pad_i (eth_rx_i[1:1]),
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.eth_rx_pad_i (eth_rx_i[1:1]),
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.eth_clk_pad_i (eth_clk_i),
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.eth_clk_pad_i (eth_clk_i),
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`endif // `ifdef USE_ETHERNET
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`endif // `ifdef USE_ETHERNET
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// SDRAM and flash memory ports
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// SDRAM and flash memory ports
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`ifdef USE_SDRAM
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`ifdef USE_SDRAM
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| Line 223... |
Line 223... |
.We_n (mem_we_o),
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.We_n (mem_we_o),
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.Dqm (mem_dqm_o));
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.Dqm (mem_dqm_o));
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|
|
`endif // !`ifdef USE_SDRAM
|
`endif // !`ifdef USE_SDRAM
|
|
|
|
`ifdef USE_ETHERNET
|
|
|
|
reg eth_clk;
|
|
initial
|
|
eth_clk <= 0;
|
|
|
|
always
|
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#(8/2) eth_clk <= ~eth_clk; // 125 Mhz clock
|
|
|
|
assign eth_clk_i = eth_clk;
|
|
|
|
|
|
|
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wire [3:0] ethphy_mii_tx_d;
|
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wire ethphy_mii_tx_en;
|
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wire ethphy_mii_tx_err;
|
|
wire mcoll_o;
|
|
wire mcrs_o;
|
|
wire md_io;
|
|
wire mrx_clk_o;
|
|
wire [3:0] mrxd_o;
|
|
wire mrxdv_o;
|
|
wire mrxerr_o;
|
|
wire mtx_clk_o;
|
|
wire smii_rx;
|
|
wire fast_ethernet, duplex, link;
|
|
|
|
/* Converts SMII back to MII */
|
|
smii_phy smii_phyend
|
|
(
|
|
// Outputs
|
|
.smii_rx (eth_rx_i[1:1]), /* SMII RX */
|
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.ethphy_mii_tx_d (ethphy_mii_tx_d[3:0]), /* MII TX */
|
|
.ethphy_mii_tx_en (ethphy_mii_tx_en), /* MII TX */
|
|
.ethphy_mii_tx_err (ethphy_mii_tx_err), /* MII TX */
|
|
// Inputs
|
|
.smii_tx (eth_tx_o[1:1]), /* SMII TX */
|
|
.smii_sync (eth_sync_o[1:1]), /* SMII SYNC */
|
|
.ethphy_mii_tx_clk (mtx_clk_o), /* MII TX */
|
|
|
|
.ethphy_mii_rx_d (mrxd_o[3:0]), /* MII RX */
|
|
.ethphy_mii_rx_dv (mrxdv_o), /* MII RX */
|
|
.ethphy_mii_rx_err (mrxerr_o), /* MII RX */
|
|
.ethphy_mii_rx_clk (mrx_clk_o), /* MII RX */
|
|
|
|
.ethphy_mii_mcoll (),
|
|
.ethphy_mii_crs (mcrs_o),
|
|
.fast_ethernet (fast_ethernet),
|
|
.duplex (duplex),
|
|
.link (link),
|
|
.clk (eth_clk_i),
|
|
.rst_n (rst_i));
|
|
|
|
`ifdef ENABLE_ETH_STIM
|
|
/* Generates an RX packet */
|
|
`include "eth_stim.v"
|
|
`endif
|
|
|
|
eth_phy eth_phy0
|
|
(
|
|
// Outputs
|
|
.mtx_clk_o (mtx_clk_o),
|
|
.mrx_clk_o (mrx_clk_o),
|
|
.mrxd_o (mrxd_o[3:0]),
|
|
.mrxdv_o (mrxdv_o),
|
|
.mrxerr_o (mrxerr_o),
|
|
.mcoll_o (mcoll_o),
|
|
.mcrs_o (mcrs_o),
|
|
// Sideband outputs for smii converter --jb
|
|
.link_o (link),
|
|
.speed_o (fast_ethernet),
|
|
.duplex_o (duplex),
|
|
// Inouts
|
|
.md_io (eth_md_io[1:1]),
|
|
// Inputs
|
|
.m_rst_n_i (rst_i),
|
|
.mtxd_i (ethphy_mii_tx_d[3:0]),
|
|
.mtxen_i (ethphy_mii_tx_en),
|
|
.mtxerr_i (ethphy_mii_tx_err),
|
|
.mdc_i (eth_mdc_o[1:1]));
|
|
|
|
`endif // `ifdef USE_ETHERNET
|
|
|
|
|
initial
|
initial
|
begin
|
begin
|
$display("\nStarting RTL simulation of %s test\n", `TEST_NAME_STRING);
|
$display("\nStarting RTL simulation of %s test\n", `TEST_NAME_STRING);
|
`ifdef USE_SDRAM
|
`ifdef USE_SDRAM
|
