URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 397 and 403

Rev 397	Rev 403
Line 43...	Line 43...

`reg clk = 0;`	`reg clk = 0;`
`reg rst_n = 1; // Active LOW`	`reg rst_n = 1; // Active LOW`

`always`	`always`
#((`BOARD_CLOCK_PERIOD_NS)/2) clk <= ~clk;	#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;

`// Reset, ACTIVE LOW`	`// Reset, ACTIVE LOW`
`initial`	`initial`
`begin`	`begin`
`#1;`	`#1;`
Line 94...	Line 94...
`or1200_monitor monitor();`	`or1200_monitor monitor();`

`ifndef SIM_QUIET	`ifndef SIM_QUIET
`define CPU_ic_top or1200_ic_top	`define CPU_ic_top or1200_ic_top
`define CPU_dc_top or1200_dc_top	`define CPU_dc_top or1200_dc_top
`wire ic_en = orpsoc_testbench.dut.or1200_top.or1200_ic_top.ic_en;`	`wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;`
`always @(posedge ic_en)`	`always @(posedge ic_en)`
`$display("Or1200 IC enabled at %t", $time);`	`$display("Or1200 IC enabled at %t", $time);`

`wire dc_en = orpsoc_testbench.dut.or1200_top.or1200_dc_top.dc_en;`	`wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;`
`always @(posedge dc_en)`	`always @(posedge dc_en)`
`$display("Or1200 DC enabled at %t", $time);`	`$display("Or1200 DC enabled at %t", $time);`
`endif	`endif


Line 126...	Line 126...


`initial`	`initial`
`begin`	`begin`
`ifndef SIM_QUIET	`ifndef SIM_QUIET
`$display("\n* Starting simulation of design RTL.\n* Test: %s\n",`	`$display("\n* Starting simulation of ORPSoC RTL.\n* Test: %s\n",`
`TEST_NAME_STRING );	`TEST_NAME_STRING );
`endif	`endif

`ifdef VCD	`ifdef VCD
`ifdef VCD_DELAY	`ifdef VCD_DELAY