| Line 42... |
Line 42... |
module smii_phy
|
module smii_phy
|
(
|
(
|
// SMII
|
// SMII
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input smii_tx,
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input smii_tx,
|
input smii_sync,
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input smii_sync,
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output smii_rx,
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output reg smii_rx,
|
|
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// MII
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// MII
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// TX
|
// TX
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/* ALL I/Os swapped compared to SMII on MAC end MAC - jb */
|
/* ALL I/Os swapped compared to SMII on MAC end MAC - jb */
|
output reg [3:0] ethphy_mii_tx_d,
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output reg [3:0] ethphy_mii_tx_d,
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| Line 88... |
Line 88... |
|
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/* Generate the state counter, based on incoming sync signal */
|
/* Generate the state counter, based on incoming sync signal */
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/* 10-bit shift register, indicating where we are */
|
/* 10-bit shift register, indicating where we are */
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reg [10:1] state_shiftreg;
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reg [10:1] state_shiftreg;
|
|
|
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/* A wire hooked up from bit 0 with the last byte of the state counter/shiftreg */
|
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wire [7:0] state_shiftreg_top_byte;
|
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assign state_shiftreg_top_byte[7:0] = state_shiftreg[10:3];
|
|
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always @(posedge clk)
|
always @(posedge clk)
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begin
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begin
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if (!rst_n)
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if (!rst_n)
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begin
|
begin
|
state_shiftreg <= 10'b0000000001;
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state_shiftreg <= 10'b0000000001;
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| Line 125... |
Line 129... |
if (segment_ctr == 4'h9) /* Wrap */
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if (segment_ctr == 4'h9) /* Wrap */
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segment_ctr <= 4'h0;
|
segment_ctr <= 4'h0;
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else /* Increment */
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else /* Increment */
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segment_ctr <= segment_ctr + 1'b1;
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segment_ctr <= segment_ctr + 1'b1;
|
end
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end
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end
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end // always @ (posedge clk)
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|
|
|
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/**************************************************************************/
|
/**************************************************************************/
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/* RX path logic PHY->(MII->SMII)->MAC */
|
/* RX path logic PHY->(MII->SMII)->MAC */
|
/**************************************************************************/
|
/**************************************************************************/
|
|
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reg rx_nibble_sel, rx_byte_valid;
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reg rx_nibble_sel, rx_byte_valid;
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reg [7:0] rx_data_byte_rx_clk;
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reg [7:0] rx_data_byte_rx_clk;
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|
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/* Receive the RX data from the PHY and serialise it */
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reg [4:0] rx_dv_nib_0;
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/* If RX data valid goes high, then it's the beginning of a
|
reg rx_nib_first,rx_nib_first_r; // if high, nib_0 contains the "first" of the pair of nibs
|
proper data segment*/
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reg [3:0] rx_segment_begin_num;
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|
|
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// Allow us to check if RX DV has been low for a while
|
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reg [3:0] rx_dv_long_low_sr;
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wire dv_long_low;
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always @(posedge ethphy_mii_rx_clk)
|
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rx_dv_long_low_sr[3:0] <= {rx_dv_long_low_sr[2:0], ethphy_mii_rx_dv};
|
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assign rx_dv_long_low = ~(|rx_dv_long_low_sr);
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reg rx_dv;
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wire [8:0] rx_fifo_out;
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wire rx_fifo_empty,rx_fifo_almost_empty;
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reg rx_fifo_pop;
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|
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always @(posedge ethphy_mii_rx_clk or negedge rst_n)
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always @(posedge ethphy_mii_rx_clk or negedge rst_n)
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begin
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begin
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if(!rst_n)
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if(!rst_n)
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begin
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begin
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rx_nibble_sel <= 0; /* start with low nibble receiving */
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rx_dv_nib_0 <= 0;
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rx_data_byte_rx_clk <= 0;
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rx_nib_first <= 0;
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rx_byte_valid <= 0;
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rx_nib_first_r <= 0;
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end
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end
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else
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else
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begin
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begin
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/* Half way through, and at the end of each 10-bit section
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if (!rx_nib_first)
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and whenever we should load a new segment (each time for
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rx_dv_nib_0 <= {ethphy_mii_rx_dv,ethphy_mii_rx_d};
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fast ethernet, else once every 10 times; whenever segment_ctr
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if(ethphy_mii_rx_dv)
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is 0)*/
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rx_nib_first <= ~rx_nib_first;
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//if ((state_shiftreg[6] | state_shiftreg[10]) & (segment_ctr==4'h0))
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// begin
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/* Alternate the nibble we're selecting when RX_dv */
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if(!ethphy_mii_rx_dv) /* data on rx line is not valid */
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rx_nibble_sel <= 0;
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else
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rx_nibble_sel <= ~rx_nibble_sel;
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|
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if (!ethphy_mii_rx_dv & !rx_nibble_sel)
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rx_nib_first_r <= rx_nib_first;
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rx_byte_valid <= 0;
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else if (rx_nibble_sel) /* sampled high nibble, byte OK*/
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rx_byte_valid <= 1;
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|
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if (ethphy_mii_rx_dv & !rx_nibble_sel)
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/* Sampling low nibble */
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rx_data_byte_rx_clk[3:0] <= ethphy_mii_rx_d;
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else if (ethphy_mii_rx_dv & rx_nibble_sel)
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/* Sample high nibble */
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rx_data_byte_rx_clk[7:4] <= ethphy_mii_rx_d;
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|
|
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//end // if ((state_shiftreg[4] | state_shiftreg[9]) & (segment_ctr==4'h0))
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end
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end // else: !if(!rst_n)
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end // always @ (posedge ethphy_mii_rx_clk or negedge rst_n)
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end // always @ (posedge clk)'
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|
|
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/* SMII domain RX signals */
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always @(posedge clk or negedge rst_n)
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reg [7:0] rx_data_byte;
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begin
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reg rx_line_rx_dv; /* Reg for second bit of SMII RX sequence, RX_DV */
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if (!rst_n) rx_fifo_pop <= 0;
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else rx_fifo_pop <= (rx_fifo_almost_empty) ? (rx_fifo_pop ? ~rx_fifo_empty : rx_fifo_pop) : 1;
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|
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/* A wire hooked up from bit 0 with the last byte of the state counter/shiftreg */
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rx_dv <= (state_shiftreg[10] & (((rx_segment_begin_num == (segment_ctr-1)) && !fast_ethernet)| fast_ethernet)) ? (rx_fifo_pop) : rx_dv;
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wire [7:0] state_shiftreg_top_byte;
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end
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assign state_shiftreg_top_byte[7:0] = state_shiftreg[10:3];
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|
|
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/* Move RX's DV and data into SMII clk domain */
|
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always @(posedge clk)
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always @(posedge clk)
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begin
|
begin
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if(!rst_n)
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/* remember which counter value we were at when rx enable/valid
|
begin
|
went high.
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rx_line_rx_dv <= 0;
|
This is only useful when not doing fast ethernet*/
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end
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else
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/* rx en has gone high - remember the sequence number we're in */
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begin
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if ((rx_segment_begin_num == 4'hf) & (~rx_dv_long_low))
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/* When we're at the beginning of a new 10-bit sequence and
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rx_segment_begin_num <= segment_ctr;
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the beginning of the 10-segment loop load the valid bit */
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if(state_shiftreg[1] & (segment_ctr==4'h0))
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/* If rx enable goes low again, reset the segment number */
|
begin
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if (rx_dv_long_low)
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rx_line_rx_dv <= rx_byte_valid;
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/* reset to 0xf */
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rx_data_byte <= rx_data_byte_rx_clk;
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rx_segment_begin_num <= 4'hf;
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end
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end
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end // else: !if(!rst_n)
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end // always @ (posedge clk)
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|
|
|
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/* A fifo, storing RX bytes coming from the PHY interface */
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generic_fifo #(9, 64) rx_fifo
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|
(
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// Outputs
|
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.psh_full (),
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.pop_q (rx_fifo_out),
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.pop_empty (rx_fifo_empty),
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.almost_empty (rx_fifo_almost_empty),
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// Inputs
|
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.async_rst_n (rst_n),
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.psh_clk (ethphy_mii_rx_clk),
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.psh_we (rx_nib_first_r),
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.psh_d ({ethphy_mii_rx_err,ethphy_mii_rx_d,rx_dv_nib_0[3:0]}),
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.pop_clk (clk),
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.pop_re ((state_shiftreg[1] & rx_fifo_pop)&(((rx_segment_begin_num == segment_ctr) && !fast_ethernet)| fast_ethernet)));
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`ifdef RX_SYNC_1
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|
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/* Assign the rx line out */
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/* Assign the rx line out */
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assign smii_rx = state_shiftreg[1] ? ethphy_mii_crs : /* 1st bit is MII CRS */
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always @(posedge clk)
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/* next is RX_DV bit */
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smii_rx <= state_shiftreg[1] ? ethphy_mii_crs : /* 1st bit is MII CRS */
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state_shiftreg[2] ? ((rx_byte_valid & (segment_ctr==4'h0)) |
|
state_shiftreg[2] ? ((rx_dv & (segment_ctr==4'h0) & !fast_ethernet) |
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rx_line_rx_dv) :
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rx_dv) :
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/* Depending on RX_DV, output the status byte or data byte */
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// inter-frame status byte or data byte
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rx_line_rx_dv ? |(state_shiftreg_top_byte & rx_data_byte) :
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state_shiftreg[3] ? (rx_dv ? (rx_fifo_out[0]) : ethphy_mii_rx_err) :
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/* Output status byte */
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state_shiftreg[4] ? (rx_dv ? (rx_fifo_out[1]) : fast_ethernet) :
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|(state_shiftreg_top_byte &
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state_shiftreg[5] ? (rx_dv ? (rx_fifo_out[2]) : duplex) :
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state_shiftreg[6] ? (rx_dv ? (rx_fifo_out[3]) : link) :
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state_shiftreg[7] ? (rx_dv ? (rx_fifo_out[4]) : jabber) :
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state_shiftreg[8] ? (rx_dv ? (rx_fifo_out[5]) : 1) :
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state_shiftreg[9] ? (rx_dv ? (rx_fifo_out[6]) : 0) :
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state_shiftreg[10] ? (rx_dv ? (rx_fifo_out[7]) : 1) : 0;
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`else // !`ifdef RX_SYNC_1
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/* Assign the rx line out */
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always @(posedge clk)
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smii_rx <= state_shiftreg[10] ? ethphy_mii_crs : /* 1st bit is MII CRS */
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state_shiftreg[1] ? ((rx_dv & (segment_ctr==4'h0) & !fast_ethernet) |
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rx_dv) :
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// inter-frame status byte or data byte
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state_shiftreg[2] ? (rx_dv ? (rx_fifo_out[0]) : ethphy_mii_rx_err) :
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state_shiftreg[3] ? (rx_dv ? (rx_fifo_out[1]) : fast_ethernet) :
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state_shiftreg[4] ? (rx_dv ? (rx_fifo_out[2]) : duplex) :
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state_shiftreg[5] ? (rx_dv ? (rx_fifo_out[3]) : link) :
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state_shiftreg[6] ? (rx_dv ? (rx_fifo_out[4]) : jabber) :
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state_shiftreg[7] ? (rx_dv ? (rx_fifo_out[5]) : 1) :
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state_shiftreg[8] ? (rx_dv ? (rx_fifo_out[6]) : 0) :
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state_shiftreg[9] ? (rx_dv ? (rx_fifo_out[7]) : 1) : 0;
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`endif // !`ifdef RX_SYNC_1
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/* Status seq.: CRS, DV, ER, Speed, Duplex, Link, Jabber, UPV, FCD, 1 */
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/* Status seq.: CRS, DV, ER, Speed, Duplex, Link, Jabber, UPV, FCD, 1 */
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{1'b1,1'b0,1'b1,jabber,link,duplex,fast_ethernet,ethphy_mii_rx_err});
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// {1'b1,1'b0,1'b1,jabber,link,duplex,,ethphy_mii_rx_err});
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/**************************************************************************/
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/**************************************************************************/
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/* TX path logic MAC->(SMII->MII)->PHY */
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/* TX path logic MAC->(SMII->MII)->PHY */
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/**************************************************************************/
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/**************************************************************************/
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|
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| Line 227... |
Line 270... |
/* Register the sequence appropriately as it comes in */
|
/* Register the sequence appropriately as it comes in */
|
reg tx_er_seqbit_scratch;
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reg tx_er_seqbit_scratch;
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reg tx_en_seqbit_scratch;
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reg tx_en_seqbit_scratch;
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reg [7:0] tx_data_byte_scratch;
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reg [7:0] tx_data_byte_scratch;
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|
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reg [1:0] tx_byte_to_phy; /* PHY sourced TX_CLK domain */
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reg [2:0] tx_byte_to_phy; /* PHY sourced TX_CLK domain */
|
|
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wire tx_fifo_empty;
|
wire tx_fifo_empty, tx_fifo_almost_empty;
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wire tx_fifo_full;
|
wire tx_fifo_full;
|
wire [7:0] tx_fifo_q_dat;
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wire [7:0] tx_fifo_q_dat;
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wire tx_fifo_q_err;
|
wire tx_fifo_q_err;
|
reg tx_fifo_pop;
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reg tx_fifo_pop;
|
|
reg [3:0] tx_segment_begin_num;
|
|
wire [3:0] tx_segment_load_num;
|
|
|
|
assign tx_segment_load_num = (tx_segment_begin_num == 0) ? 4'h9 : tx_segment_begin_num - 1;
|
|
|
/* Signal to tell us an appropriate time to copy the values out of the
|
/* Signal to tell us an appropriate time to copy the values out of the
|
temp regs we put the incoming TX line into when we've received a
|
temp regs we put the incoming TX line into when we've received a
|
sequence off the SMII TX line that has TX_EN high */
|
sequence off the SMII TX line that has TX_EN high */
|
wire tx_seqbits_copy;
|
wire tx_seqbits_copy;
|
assign tx_seqbits_copy = ((((!fast_ethernet) & (segment_ctr==4'h1)) |
|
assign tx_seqbits_copy = (
|
((fast_ethernet) & (state_shiftreg[1])))
|
(
|
& tx_en_seqbit_scratch);
|
((!fast_ethernet) & (segment_ctr == tx_segment_load_num)) |
|
|
fast_ethernet
|
|
)
|
|
& tx_en_seqbit_scratch & state_shiftreg[1]
|
|
);
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
/* remember which counter value we were at when tx enable/valid
|
|
went high.
|
|
This is only useful when not doing fast ethernet*/
|
|
|
|
/* tx en has gone high - remember the sequence number we're in */
|
|
if ((tx_segment_begin_num == 4'hf) & (tx_en_seqbit_scratch))
|
|
tx_segment_begin_num <= segment_ctr;
|
|
|
|
/* If tx enable goes low again, reset the segment number */
|
|
if (!tx_en_seqbit_scratch)
|
|
/* reset to 0xf */
|
|
tx_segment_begin_num <= 4'hf;
|
|
end
|
|
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (!rst_n)
|
if (!rst_n)
|
begin
|
begin
|
| Line 254... |
Line 321... |
tx_en_seqbit_scratch <= 0;
|
tx_en_seqbit_scratch <= 0;
|
tx_data_byte_scratch <= 0;
|
tx_data_byte_scratch <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (segment_ctr==4'h0)
|
|
begin
|
|
if(state_shiftreg[1])
|
if(state_shiftreg[1])
|
tx_er_seqbit_scratch <= smii_tx;
|
tx_er_seqbit_scratch <= smii_tx;
|
|
|
if(state_shiftreg[2])
|
if(state_shiftreg[2])
|
tx_en_seqbit_scratch <= smii_tx;
|
tx_en_seqbit_scratch <= smii_tx;
|
| Line 270... |
Line 335... |
position*/
|
position*/
|
if((|state_shiftreg[10:3]) & tx_en_seqbit_scratch)
|
if((|state_shiftreg[10:3]) & tx_en_seqbit_scratch)
|
tx_data_byte_scratch <= (tx_data_byte_scratch & ~state_shiftreg_top_byte) |
|
tx_data_byte_scratch <= (tx_data_byte_scratch & ~state_shiftreg_top_byte) |
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({8{smii_tx}} & state_shiftreg_top_byte);
|
({8{smii_tx}} & state_shiftreg_top_byte);
|
|
|
end // if (segment_ctr==4'h0)
|
|
|
|
/* If we've just received a sequence with TX_EN then put
|
|
these values in the proper regs at the appropriate time,
|
|
depending on the speed , ready for transmission to the PHY */
|
|
if (tx_seqbits_copy)
|
|
begin
|
|
|
|
/* Now clear the tx_en scratch bit so we don't do
|
|
this again */
|
|
tx_en_seqbit_scratch <= 0;
|
|
|
|
end // if (tx_seqbits_copy)
|
|
end
|
end
|
end // always @ (posedge clk)
|
end // always @ (posedge clk)
|
|
|
|
reg [3:0] nib;
|
|
|
|
|
|
|
/* In the event we have a valid byte frame then get it to the
|
/* In the event we have a valid byte frame then get it to the
|
PHY as quickly as possible - this is TX_CLK domain */
|
PHY as quickly as possible - this is TX_CLK domain */
|
always @(posedge ethphy_mii_tx_clk or negedge rst_n)
|
always @(posedge ethphy_mii_tx_clk or negedge rst_n)
|
begin
|
begin
|
| Line 303... |
Line 358... |
ethphy_mii_tx_err <= 0;
|
ethphy_mii_tx_err <= 0;
|
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
/* If fast_ethernet/100mbs we wait until the FIFO is full
|
if(!tx_fifo_empty) /* A byte ready to go to the MAC */
|
otherwise, we push out the byte each time we get one */
|
|
//if((!tx_fifo_empty && !fast_ethernet) ||
|
|
//(tx_fifo_full && fast_ethernet))
|
|
if (!tx_fifo_almost_empty)
|
begin
|
begin
|
if(tx_byte_to_phy == 2'b00)
|
if(tx_byte_to_phy == 0)
|
begin
|
begin
|
/* Pop */
|
tx_byte_to_phy <= 1;
|
tx_fifo_pop <= 1;
|
tx_fifo_pop <= 1;
|
tx_byte_to_phy <= 2'b01;
|
|
end
|
end
|
end
|
end
|
|
|
/* FIFO control loop */
|
/* FIFO control loop */
|
if (tx_byte_to_phy == 2'b01) /* Output bits 3-0 (bottom nibble ) */
|
if (tx_byte_to_phy == 1)/* Output bits 3-0 (bottom nibble ) */
|
begin
|
begin
|
ethphy_mii_tx_d <= tx_fifo_q_dat[3:0];
|
|
ethphy_mii_tx_en <= 1;
|
ethphy_mii_tx_en <= 1;
|
ethphy_mii_tx_err <= tx_fifo_q_err;
|
|
tx_fifo_pop <= 0;
|
tx_fifo_pop <= 0;
|
tx_byte_to_phy <= 2'b10;
|
|
|
tx_byte_to_phy <= 2;
|
|
|
|
ethphy_mii_tx_d <= tx_fifo_q_dat[3:0];
|
|
nib <= tx_fifo_q_dat[7:4];
|
|
ethphy_mii_tx_err <= tx_fifo_q_err;
|
|
|
end
|
end
|
else if (tx_byte_to_phy == 2'b10) /* Output bits 7-4 (top nibble) */
|
else if (tx_byte_to_phy == 2) /* Output bits 7-4 (top nibble) */
|
begin
|
begin
|
ethphy_mii_tx_d <= tx_fifo_q_dat[7:4];
|
//ethphy_mii_tx_d <= tx_fifo_q_dat[7:4];
|
|
|
|
ethphy_mii_tx_d <= nib;
|
|
|
if(!tx_fifo_empty) /* Check if more in FIFO */
|
if(!tx_fifo_empty) /* Check if more in FIFO */
|
begin
|
begin
|
tx_fifo_pop <= 1; /* Pop again */
|
tx_fifo_pop <= 1;
|
tx_byte_to_phy <= 2'b01;
|
tx_byte_to_phy <= 1;
|
end
|
end
|
else /* Finish up */
|
else /* Finish up */
|
begin
|
begin
|
tx_byte_to_phy <= 2'b11;
|
tx_byte_to_phy <= 3;
|
|
ethphy_mii_tx_en <= 0;
|
end
|
end
|
end
|
end
|
else if (tx_byte_to_phy == 2'b11) /* De-assert TX_EN */
|
else if (tx_byte_to_phy == 3) /* De-assert TX_EN */
|
begin
|
begin
|
ethphy_mii_tx_en <= 0;
|
|
tx_byte_to_phy <= 2'b00;
|
tx_byte_to_phy <= 2'b00;
|
end
|
end
|
end // else: !if(!rst_n)
|
end // else: !if(!rst_n)
|
end // always @ (posedge ethphy_mii_tx_clk or negedge rst_n)
|
end // always @ (posedge ethphy_mii_tx_clk or negedge rst_n)
|
|
|
| Line 351... |
Line 417... |
(
|
(
|
// Outputs
|
// Outputs
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.psh_full (tx_fifo_full),
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.psh_full (tx_fifo_full),
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.pop_q ({tx_fifo_q_err,tx_fifo_q_dat}),
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.pop_q ({tx_fifo_q_err,tx_fifo_q_dat}),
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.pop_empty (tx_fifo_empty),
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.pop_empty (tx_fifo_empty),
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.almost_empty (tx_fifo_almost_empty),
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// Inputs
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// Inputs
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.async_rst_n (rst_n),
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.async_rst_n (rst_n),
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.psh_clk (clk),
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.psh_clk (clk),
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.psh_we (tx_seqbits_copy),
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.psh_we (tx_seqbits_copy),
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.psh_d ({tx_er_seqbit_scratch,tx_data_byte_scratch}),
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.psh_d ({tx_er_seqbit_scratch,tx_data_byte_scratch}),
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.pop_clk (),
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.pop_clk (ethphy_mii_tx_clk),
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.pop_re (tx_fifo_pop));
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.pop_re (tx_fifo_pop));
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//assign mcoll = mcrs & mtxen;
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//assign mcoll = mcrs & mtxen;
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endmodule // smii_top
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endmodule // smii_top
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/* Generic fifo - this is bad, should probably be done some other way */
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/* Generic fifo - this is bad, should probably be done some other way */
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module generic_fifo (async_rst_n, psh_clk, psh_we, psh_d, psh_full, pop_clk, pop_re, pop_q, pop_empty);
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module generic_fifo (async_rst_n, psh_clk, psh_we, psh_d, psh_full, pop_clk, pop_re, pop_q, pop_empty, almost_empty);
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parameter dw = 8;
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parameter dw = 8;
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parameter size = 64;
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parameter size = 16;
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parameter size_log_2 = 4;
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/* Asynch. reset, active low */
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/* Asynch. reset, active low */
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input async_rst_n;
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input async_rst_n;
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/* Push side signals */
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/* Push side signals */
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| Line 384... |
Line 452... |
output psh_full;
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output psh_full;
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/* Pop side signals */
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/* Pop side signals */
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input pop_clk;
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input pop_clk;
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input pop_re;
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input pop_re;
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//output reg [dw-1:0] pop_q;
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output reg [dw-1:0] pop_q;
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output reg [dw-1:0] pop_q;
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output pop_empty;
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output pop_empty;
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output wire almost_empty;
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/* Actual FIFO memory */
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/* Actual FIFO memory */
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reg [dw-1:0] fifo_mem [0:size-1];
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reg [dw-1:0] fifo_mem [0:size-1];
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/* Poorly defined pointer logic -- will need to be changed if the size paramter is too big - Verilog needs some log base 2 thing */
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reg [7:0] ptr; /* Only 8 bits, so max size of 255 of fifo! */
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/* FIFO position ptr regs */
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reg [size_log_2 - 1 : 0 ] wr_ptr, rd_ptr, ctr;
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/* FIFO full signal for push side */
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integer i;
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assign psh_full = (ptr == size-1) ? 1 : 0;
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/* FIFO empty signal for pop side */
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assign pop_empty = (ptr == 0) ? 1 : 0;
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/* This will work if pushing side is a lot faster than popping side */
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/* FIFO full signal for push side */
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reg pop_re_psh_clk;
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//assign psh_full = (ptr == size-1) ? 1 : 0;
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wire pop_re_risingedge_psh_clk; /* Signal to help push side see when
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/* This full logic means we all but one slot in the FIFO */
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there's been a pop_re rising edge,
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assign psh_full = ctr == size;
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sampled on push clock */
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/* Detect edge of signal in pop domain for psh domain */
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/* FIFO empty signal for pop side */
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assign pop_re_risingedge_psh_clk = (pop_re & !pop_re_psh_clk);
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//assign pop_empty = (ptr == 0) ? 1 : 0;
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//assign pop_empty = ctr==0;
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assign pop_empty = rd_ptr == wr_ptr;
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assign almost_empty = ctr < 2;
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integer i;
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always @(posedge pop_re or negedge async_rst_n)
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always @(posedge psh_clk or negedge async_rst_n)
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begin
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begin
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if (!async_rst_n)
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if (!async_rst_n)
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rd_ptr <= 0;
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else
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begin
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begin
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ptr <= 0;
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pop_q = fifo_mem[rd_ptr];
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rd_ptr <= rd_ptr + 1;
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ctr <= ctr - 1;
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end
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end
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always @(posedge psh_we or negedge async_rst_n)
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begin
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if (!async_rst_n)
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begin
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for (i=0;i<size;i=i+1) fifo_mem[i] <= 0;
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for (i=0;i<size;i=i+1) fifo_mem[i] <= 0;
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wr_ptr <= 0;
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pop_re_psh_clk <= 0;
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ctr <= 0;
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end
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end
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else
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else
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begin
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begin
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fifo_mem[wr_ptr] <= psh_d;
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pop_re_psh_clk <= pop_re; /* Register pop command in psh domain */
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wr_ptr <= #1 wr_ptr + 1;
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ctr <= ctr + 1;
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if (psh_we) /* Push into FIFO */
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end
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begin
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if (!pop_re_psh_clk) /* If no pop at the same time, simple */
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begin
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fifo_mem[ptr] <= psh_d;
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ptr <= ptr + 1'b1;
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end
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end
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else /* Pop at same edge */
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begin
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/* Shift fifo contents */
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for(i=1;i<size;i=i+1)
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fifo_mem[i-1] <= fifo_mem[i];
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fifo_mem[size-1] <= 0;
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pop_q <= fifo_mem[0];
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fifo_mem[ptr] <= psh_d;
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/* ptr remains unchanged */
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end // else: !if!(pop_re_psh_clk)
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end // if (psh_we)
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else /* No push, see if there's a pop */
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begin
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if (pop_re_risingedge_psh_clk) /* Detected a pop */
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begin
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for(i=1;i<size;i=i+1)
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fifo_mem[i-1] <= fifo_mem[i];
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fifo_mem[size-1] <= 0;
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pop_q <= fifo_mem[0];
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ptr <= ptr - 1'b1;
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end
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end // else: !if(psh_we)
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end // else: !if(!async_rst_n)
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end // always @ (posedge psh_clk or negedge async_rst_n)
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endmodule // generic_fifo
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endmodule // generic_fifo
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