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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [uart_decoder.v] - Diff between revs 65 and 354

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//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// Decodes UART signals sent over the line defined by UART_TX_LINE
 
 
 
// `include this file in the testbench and define UART_TX_LINE
 
// Uses define CLOCK_RATE as the frequency of the clock in Hz
 
 
 
// Receieves and decodes 8-bit,  1 stop bit, no parity UART signals.
// Receieves and decodes 8-bit,  1 stop bit, no parity UART signals.
 
`timescale 1ns/1ns
 
module uart_decoder(clk, uart_tx);
 
 
// Requires definition of:
   input clk;
// CLK_RATE - frequency of system clock in Hz
   input uart_tx;
// CLK_PERIOD - period of clock frequency in ns
 
// UART_BAUDRATE - otherwise defaults to 115200
 
// UART_TX_LINE - name of the UART output signal (normally a wire)
 
 
 
// if it's not already defined, uses UART_BAUDRATE as baud to receive
 
// bytes at
 
`ifndef UART_BAUDRATE
 
 `define UART_BAUDRATE 115200
 
`endif
 
 
 
`ifndef CLOCK_RATE
   // Default baud of 115200, period (ns)
initial
   parameter uart_baudrate_period_ns = 8680;
  begin
 
     $display("* WARNING: uart_decoder included but CLOCK_RATE not defined.");
 
  end
 
`else
 
 `ifdef UART_TX_LINE
 
   parameter UART_TX_WAIT = (`CLOCK_RATE / `UART_BAUDRATE) * `CLOCK_PERIOD;
 
 
 
   // Something to trigger the task
   // Something to trigger the task
   always @(posedge clk)
   always @(posedge clk)
     uart_decoder;
     uart_decoder;
 
 
   task uart_decoder;
   task uart_decoder;
      reg [7:0] tx_byte;
      reg [7:0] tx_byte;
      begin
      begin
 
         while (uart_tx !== 1'b1)
         while (`UART_TX_LINE !== 1'b1)
           @(uart_tx);
           @(`UART_TX_LINE);
 
         // Wait for start bit
         // Wait for start bit
         //while (`UART_TX_LINE == 1'b1)
         while (uart_tx !== 1'b0)
         while (`UART_TX_LINE !== 1'b0)
           @(uart_tx);
           @(`UART_TX_LINE);
         #(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
         #(UART_TX_WAIT+(UART_TX_WAIT/2));
         tx_byte[0] = uart_tx;
         tx_byte[0] = `UART_TX_LINE;
         #uart_baudrate_period_ns;
         #UART_TX_WAIT;
         tx_byte[1] = uart_tx;
         tx_byte[1] = `UART_TX_LINE;
         #uart_baudrate_period_ns;
         #UART_TX_WAIT;
         tx_byte[2] = uart_tx;
         tx_byte[2] = `UART_TX_LINE;
         #uart_baudrate_period_ns;
         #UART_TX_WAIT;
         tx_byte[3] = uart_tx;
         tx_byte[3] = `UART_TX_LINE;
         #uart_baudrate_period_ns;
         #UART_TX_WAIT;
         tx_byte[4] = uart_tx;
         tx_byte[4] = `UART_TX_LINE;
         #uart_baudrate_period_ns;
         #UART_TX_WAIT;
         tx_byte[5] = uart_tx;
         tx_byte[5] = `UART_TX_LINE;
         #uart_baudrate_period_ns;
         #UART_TX_WAIT;
         tx_byte[6] = uart_tx;
         tx_byte[6] = `UART_TX_LINE;
         #uart_baudrate_period_ns;
         #UART_TX_WAIT;
         tx_byte[7] = uart_tx;
         tx_byte[7] = `UART_TX_LINE;
         #uart_baudrate_period_ns;
         #UART_TX_WAIT;
 
         //Check for stop bit
         //Check for stop bit
         //if (`UART_TX_LINE == 1'b0)
         if (uart_tx !== 1'b1)
         if (`UART_TX_LINE !== 1'b1)
 
           begin
           begin
              //$display("* WARNING: user stop bit not received when expected at time %d__", $time);
 
              // Wait for return to idle
              // Wait for return to idle
              //while (`UART_TX_LINE == 1'b0)
              while (uart_tx !== 1'b1)
              while (`UART_TX_LINE !== 1'b1)
                @(uart_tx);
                @(`UART_TX_LINE);
 
              //$display("* USER UART returned to idle at time %d",$time);
 
           end
           end
         // display the char
         // display the char
         $write("%c", tx_byte);
         $write("%c", tx_byte);
      end
      end
   endtask // user_uart_read_byte
   endtask // user_uart_read_byte
 `else // !`ifdef UART_TX_LINE
 
   // If this file was included but not setup properly
endmodule // uart_decoder
   initial
 
     begin
 
        $display("* WARNING: uart_decoder included but UART_TX_LINE not defined.");
 
     end
 
 `endif // !`ifdef UART_TX_LINE
 
`endif // !`ifndef CLOCK_RATE
 
 
 
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