URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [uart_decoder.v] - Diff between revs 6 and 65

Rev 6	Rev 65
Line 73...	Line 73...

`task uart_decoder;`	`task uart_decoder;`
`reg [7:0] tx_byte;`	`reg [7:0] tx_byte;`
`begin`	`begin`

	while (`UART_TX_LINE !== 1'b1)
	@(`UART_TX_LINE);
`// Wait for start bit`	`// Wait for start bit`
while (`UART_TX_LINE == 1'b1)	//while (`UART_TX_LINE == 1'b1)
	while (`UART_TX_LINE !== 1'b0)
@(`UART_TX_LINE);	@(`UART_TX_LINE);
`#(UART_TX_WAIT+(UART_TX_WAIT/2));`	`#(UART_TX_WAIT+(UART_TX_WAIT/2));`
tx_byte[0] = `UART_TX_LINE;	tx_byte[0] = `UART_TX_LINE;
`#UART_TX_WAIT;`	`#UART_TX_WAIT;`
tx_byte[1] = `UART_TX_LINE;	tx_byte[1] = `UART_TX_LINE;
Line 94...	Line 97...
tx_byte[6] = `UART_TX_LINE;	tx_byte[6] = `UART_TX_LINE;
`#UART_TX_WAIT;`	`#UART_TX_WAIT;`
tx_byte[7] = `UART_TX_LINE;	tx_byte[7] = `UART_TX_LINE;
`#UART_TX_WAIT;`	`#UART_TX_WAIT;`
`//Check for stop bit`	`//Check for stop bit`
if (`UART_TX_LINE == 1'b0)	//if (`UART_TX_LINE == 1'b0)
	if (`UART_TX_LINE !== 1'b1)
`begin`	`begin`
`//$display("* WARNING: user stop bit not received when expected at time %d__", $time);`	`//$display("* WARNING: user stop bit not received when expected at time %d__", $time);`
`// Wait for return to idle`	`// Wait for return to idle`
while (`UART_TX_LINE == 1'b0)	//while (`UART_TX_LINE == 1'b0)
	while (`UART_TX_LINE !== 1'b1)
@(`UART_TX_LINE);	@(`UART_TX_LINE);
`//$display("* USER UART returned to idle at time %d",$time);`	`//$display("* USER UART returned to idle at time %d",$time);`
`end`	`end`
`// display the char`	`// display the char`
`$write("%c", tx_byte);`	`$write("%c", tx_byte);`