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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// Decodes UART signals sent over the line defined by UART_TX_LINE
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// `include this file in the testbench and define UART_TX_LINE
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// Uses define CLOCK_RATE as the frequency of the clock in Hz
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// Receieves and decodes 8-bit, 1 stop bit, no parity UART signals.
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// Receieves and decodes 8-bit, 1 stop bit, no parity UART signals.
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`timescale 1ns/1ns
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module uart_decoder(clk, uart_tx);
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// Requires definition of:
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input clk;
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// CLK_RATE - frequency of system clock in Hz
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input uart_tx;
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// CLK_PERIOD - period of clock frequency in ns
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// UART_BAUDRATE - otherwise defaults to 115200
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// UART_TX_LINE - name of the UART output signal (normally a wire)
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// if it's not already defined, uses UART_BAUDRATE as baud to receive
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// bytes at
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`ifndef UART_BAUDRATE
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`define UART_BAUDRATE 115200
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`endif
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`ifndef CLOCK_RATE
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// Default baud of 115200, period (ns)
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initial
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parameter uart_baudrate_period_ns = 8680;
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begin
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$display("* WARNING: uart_decoder included but CLOCK_RATE not defined.");
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end
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`else
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`ifdef UART_TX_LINE
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parameter UART_TX_WAIT = (`CLOCK_RATE / `UART_BAUDRATE) * `CLOCK_PERIOD;
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// Something to trigger the task
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// Something to trigger the task
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always @(posedge clk)
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always @(posedge clk)
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uart_decoder;
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uart_decoder;
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task uart_decoder;
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task uart_decoder;
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reg [7:0] tx_byte;
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reg [7:0] tx_byte;
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begin
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begin
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while (uart_tx !== 1'b1)
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while (`UART_TX_LINE !== 1'b1)
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@(uart_tx);
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@(`UART_TX_LINE);
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// Wait for start bit
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// Wait for start bit
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//while (`UART_TX_LINE == 1'b1)
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while (uart_tx !== 1'b0)
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while (`UART_TX_LINE !== 1'b0)
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@(uart_tx);
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@(`UART_TX_LINE);
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#(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
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#(UART_TX_WAIT+(UART_TX_WAIT/2));
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tx_byte[0] = uart_tx;
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tx_byte[0] = `UART_TX_LINE;
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#uart_baudrate_period_ns;
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#UART_TX_WAIT;
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tx_byte[1] = uart_tx;
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tx_byte[1] = `UART_TX_LINE;
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#uart_baudrate_period_ns;
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#UART_TX_WAIT;
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tx_byte[2] = uart_tx;
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tx_byte[2] = `UART_TX_LINE;
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#uart_baudrate_period_ns;
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#UART_TX_WAIT;
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tx_byte[3] = uart_tx;
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tx_byte[3] = `UART_TX_LINE;
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#uart_baudrate_period_ns;
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#UART_TX_WAIT;
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tx_byte[4] = uart_tx;
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tx_byte[4] = `UART_TX_LINE;
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#uart_baudrate_period_ns;
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#UART_TX_WAIT;
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tx_byte[5] = uart_tx;
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tx_byte[5] = `UART_TX_LINE;
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#uart_baudrate_period_ns;
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#UART_TX_WAIT;
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tx_byte[6] = uart_tx;
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tx_byte[6] = `UART_TX_LINE;
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#uart_baudrate_period_ns;
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#UART_TX_WAIT;
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tx_byte[7] = uart_tx;
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tx_byte[7] = `UART_TX_LINE;
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#uart_baudrate_period_ns;
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#UART_TX_WAIT;
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//Check for stop bit
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//Check for stop bit
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//if (`UART_TX_LINE == 1'b0)
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if (uart_tx !== 1'b1)
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if (`UART_TX_LINE !== 1'b1)
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begin
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begin
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//$display("* WARNING: user stop bit not received when expected at time %d__", $time);
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// Wait for return to idle
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// Wait for return to idle
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//while (`UART_TX_LINE == 1'b0)
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while (uart_tx !== 1'b1)
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while (`UART_TX_LINE !== 1'b1)
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@(uart_tx);
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@(`UART_TX_LINE);
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//$display("* USER UART returned to idle at time %d",$time);
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end
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end
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// display the char
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// display the char
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$write("%c", tx_byte);
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$write("%c", tx_byte);
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end
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end
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endtask // user_uart_read_byte
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endtask // user_uart_read_byte
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`else // !`ifdef UART_TX_LINE
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// If this file was included but not setup properly
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endmodule // uart_decoder
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initial
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begin
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$display("* WARNING: uart_decoder included but UART_TX_LINE not defined.");
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end
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`endif // !`ifdef UART_TX_LINE
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`endif // !`ifndef CLOCK_RATE
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No newline at end of file
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No newline at end of file
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