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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.c] - Diff between revs 46 and 49

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Rev 46 Rev 49
Line 512... Line 512...
 
 
  return DBG_ERR_OK;
  return DBG_ERR_OK;
}
}
 
 
/* read a register from cpu */
/* read a register from cpu */
int dbg_cpu0_read(uint32_t adr, uint32_t *data)
int dbg_cpu0_read(uint32_t adr, uint32_t *data, uint32_t length)
{
{
 
 
  if (DBG_CALLS)printf("dbg_cpu0_read: adr 0x%.8x\n",adr);
  if (DBG_CALLS)printf("dbg_cpu0_read: adr 0x%.8x\n",adr);
 
 
  dbg_set_chain(DC_CPU0);
  dbg_set_chain(DC_CPU0);
 
 
  send_command_to_vpi(CMD_CPU_RD_REG);
  send_command_to_vpi(CMD_CPU_RD_REG);
 
 
  send_address_to_vpi(adr);
  send_address_to_vpi(adr);
 
 
  get_data_from_vpi(data);
  send_data_to_vpi(length); // Added 090901 --jb
 
 
 
  get_block_data_from_vpi(length, data); // changed 090901 --jb //get_data_from_vpi(data);
 
 
  get_response_from_vpi();
  get_response_from_vpi();
 
 
  return 0;
  return 0;
 
 
}
}
 
 
/* write a cpu register */
/* write a cpu register */
int dbg_cpu0_write(uint32_t adr, uint32_t data)
int dbg_cpu0_write(uint32_t adr, uint32_t *data, uint32_t length)
{
{
 
 
  if (DBG_CALLS)printf("dbg_cpu0_write: adr 0x%.8x\n",adr);
  if (DBG_CALLS)printf("dbg_cpu0_write: adr 0x%.8x\n",adr);
 
 
  dbg_set_chain(DC_CPU0);
  dbg_set_chain(DC_CPU0);
 
 
  send_command_to_vpi(CMD_CPU_WR_REG);
  send_command_to_vpi(CMD_CPU_WR_REG);
 
 
  send_address_to_vpi(adr);
  send_address_to_vpi(adr);
 
 
  send_data_to_vpi(data);
  send_data_to_vpi(length); // Added 090901 -- jb
 
 
 
  send_block_data_to_vpi(length, data); // Added 090901 -- jb
 
 
  get_response_from_vpi();
  get_response_from_vpi();
 
 
  return 0;
  return 0;
}
}
Line 620... Line 624...
  if (!(stalled & 0x1)) {
  if (!(stalled & 0x1)) {
    printf("\tor1k stall failed. read: 0x%x\n", stalled);   // check stall or1k
    printf("\tor1k stall failed. read: 0x%x\n", stalled);   // check stall or1k
    //exit(1);
    //exit(1);
  }
  }
 
 
  debug2("  Reading npc\n");
  /* Read NPC,PPC and SR regs, they are consecutive in CPU, at adr. 16, 17 and 18 */
  dbg_cpu0_read((0 << 11) + 16, &npc);
  uint32_t pcs_and_sr[3];
  debug2("  Reading ppc\n");
  debug2("  Reading npc, ppc\n");
  dbg_cpu0_read((0 << 11) + 18, &ppc);
  dbg_cpu0_read(16, (uint32_t *)pcs_and_sr, 3 * 4);
 
 
  debug2("  Reading r1\n");
  debug2("  Reading r1\n");
  dbg_cpu0_read(0x401, &r1);
  dbg_cpu0_read(0x401, &r1, 4);
  printf("  Read      npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
  printf("  Read      npc = %.8x ppc = %.8x r1 = %.8x\n",
 
         pcs_and_sr[0], pcs_and_sr[2], r1);
 
 
}
}
 
 
// Catch the term/int signals, close gdb then close ourselves
// Catch the term/int signals, close gdb then close ourselves
void catch_sigint(int sig_num)
void catch_sigint(int sig_num)

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